In #3721, we have been discussing what to do about the ARM32 backend in Cranelift. Currently, this backend supports only 32-bit types, which is insufficient for full Wasm-MVP; it's missing other critical bits, like floating-point support; and it has only ever been exercised, AFAIK, via the filetests for the individual CLIF instructions that are implemented. We were very very thankful for the original contribution of this backend, even in its partial state, and we had hoped at the time that we could eventually mature it in-tree until it supported e.g. Wasm and other use-cases. But that hasn't yet happened -- to the blame of no-one, to be clear, we just haven't had a contributor with sufficient time. Unfortunately, the existence of the backend and lack of active maintainer now potentially pose a bit of a burden as we hope to make continuing changes to the backend framework. For example, the ISLE migration, and the use of regalloc2 that it will allow, would need all of the existing lowering patterns in the hand-written ARM32 backend to be rewritten as ISLE rules. Given that we don't currently have the resources to do this, we think it's probably best if we, sadly, for now remove this partial backend. This is not in any way a statement of what we might accept in the future, though. If, in the future, an ARM32 backend updated to our latest codebase with an active maintainer were to appear, we'd be happy to merge it (and likewise for any other architecture!). But for now, this is probably the best path. Thanks again to the original contributor @jmkrauz and we hope that this work can eventually be brought back and reused if someone has the time to do so!
131 lines
4.1 KiB
Rust
131 lines
4.1 KiB
Rust
//! Data structure for tracking the (possibly multiple) registers that hold one
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//! SSA `Value`.
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use regalloc::{RealReg, Reg, VirtualReg, Writable};
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use std::fmt::Debug;
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const VALUE_REGS_PARTS: usize = 2;
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/// Location at which a `Value` is stored in register(s): the value is located
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/// in one or more registers, depending on its width. A value may be stored in
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/// more than one register if the machine has no registers wide enough
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/// otherwise: for example, on a 32-bit architecture, we may store `I64` values
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/// in two registers, and `I128` values in four.
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///
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/// By convention, the register parts are kept in machine-endian order here.
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///
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/// N.B.: we cap the capacity of this at four (when any 32-bit target is
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/// enabled) or two (otherwise), and we use special in-band sentinal `Reg`
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/// values (`Reg::invalid()`) to avoid the need to carry a separate length. This
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/// allows the struct to be `Copy` (no heap or drop overhead) and be only 16 or
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/// 8 bytes, which is important for compiler performance.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub struct ValueRegs<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> {
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parts: [R; VALUE_REGS_PARTS],
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}
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/// A type with an "invalid" sentinel value.
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pub trait InvalidSentinel: Copy + Eq {
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/// The invalid sentinel value.
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fn invalid_sentinel() -> Self;
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/// Is this the invalid sentinel?
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fn is_invalid_sentinel(self) -> bool {
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self == Self::invalid_sentinel()
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}
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}
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impl InvalidSentinel for Reg {
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fn invalid_sentinel() -> Self {
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Reg::invalid()
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}
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}
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impl InvalidSentinel for VirtualReg {
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fn invalid_sentinel() -> Self {
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VirtualReg::invalid()
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}
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}
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impl InvalidSentinel for RealReg {
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fn invalid_sentinel() -> Self {
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RealReg::invalid()
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}
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}
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impl InvalidSentinel for Writable<Reg> {
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fn invalid_sentinel() -> Self {
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Writable::from_reg(Reg::invalid_sentinel())
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}
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}
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impl<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> ValueRegs<R> {
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/// Create an invalid Value-in-Reg.
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pub fn invalid() -> Self {
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ValueRegs {
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parts: [R::invalid_sentinel(); VALUE_REGS_PARTS],
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}
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}
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/// Is this Value-to-Reg mapping valid?
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pub fn is_valid(self) -> bool {
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!self.parts[0].is_invalid_sentinel()
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}
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/// Is this Value-to-Reg mapping invalid?
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pub fn is_invalid(self) -> bool {
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self.parts[0].is_invalid_sentinel()
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}
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/// Return the single register used for this value, if any.
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pub fn only_reg(self) -> Option<R> {
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if self.len() == 1 {
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Some(self.parts[0])
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} else {
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None
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}
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}
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/// Return an iterator over the registers storing this value.
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pub fn regs(&self) -> &[R] {
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&self.parts[0..self.len()]
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}
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}
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impl<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> ValueRegs<R> {
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/// Create a Value-in-R location for a value stored in one register.
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pub fn one(reg: R) -> Self {
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ValueRegs {
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parts: [reg, R::invalid_sentinel()],
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}
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}
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/// Create a Value-in-R location for a value stored in two registers.
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pub fn two(r1: R, r2: R) -> Self {
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ValueRegs { parts: [r1, r2] }
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}
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/// Return the number of registers used.
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pub fn len(self) -> usize {
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// If rustc/LLVM is smart enough, this might even be vectorized...
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(self.parts[0] != R::invalid_sentinel()) as usize
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+ (self.parts[1] != R::invalid_sentinel()) as usize
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}
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/// Map individual registers via a map function.
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pub fn map<NewR, F>(self, f: F) -> ValueRegs<NewR>
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where
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NewR: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel,
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F: Fn(R) -> NewR,
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{
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ValueRegs {
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parts: [f(self.parts[0]), f(self.parts[1])],
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}
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}
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}
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/// Create a writable ValueRegs.
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#[allow(dead_code)]
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pub(crate) fn writable_value_regs(regs: ValueRegs<Reg>) -> ValueRegs<Writable<Reg>> {
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regs.map(|r| Writable::from_reg(r))
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}
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/// Strip a writable ValueRegs down to a readonly ValueRegs.
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#[allow(dead_code)]
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pub(crate) fn non_writable_value_regs(regs: ValueRegs<Writable<Reg>>) -> ValueRegs<Reg> {
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regs.map(|r| r.to_reg())
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}
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