Jakob Stoklund Olesen bd8230411a Encodings for load/store instructions. ...

We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.

2017-05-12 16:49:39 -07:00

..

arm32

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

arm64

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

intel

Encodings for load/store instructions.

2017-05-12 16:49:39 -07:00

riscv

Add an enable_e setting for the RV32E instruction set.

2017-04-26 13:50:52 -07:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00