Jakob Stoklund Olesen bd8230411a Encodings for load/store instructions. ...

We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.

2017-05-12 16:49:39 -07:00

..

base

Make srem have the sign of the dividend.

2017-05-09 12:28:15 -07:00

cdsl

Check for unknown instruction attributes. (#80)

2017-05-11 10:21:59 -07:00

isa

Encodings for load/store instructions.

2017-05-12 16:49:39 -07:00

build.py

Add a mypy.ini file and enable some more warnings.

2017-03-30 19:52:49 -07:00

check.sh

Run Python checks from test-all.sh

2017-01-25 14:12:36 -08:00

constant_hash.py

Run mypy in python 3 mode.

2017-05-08 13:29:01 -07:00

gen_binemit.py

Generate binemit::emit_inst() functions.

2017-03-28 14:44:36 -07:00

gen_build_deps.py

Add more mypy annotations.

2017-03-30 15:16:44 -07:00

gen_encoding.py

Add constraint summaries to RecipeConstraints.

2017-05-08 16:41:24 -07:00

gen_instr.py

Upgrade to Rust 1.17.

2017-04-27 12:46:44 -07:00

gen_legalizer.py

Avoid creating aliases when expanding legalizer patterns.

2017-04-13 09:30:21 -07:00

gen_registers.py

Implement legalize_signature for RISC-V.

2017-03-03 11:09:55 -08:00

gen_settings.py

Upgrade to Rust 1.17.

2017-04-27 12:46:44 -07:00

gen_types.py

Add more mypy annotations.

2017-03-30 15:16:44 -07:00

mypy.ini

Run mypy in python 3 mode.

2017-05-08 13:29:01 -07:00

srcgen.py

Add more mypy annotations.

2017-03-30 15:16:44 -07:00

test_constant_hash.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

test_srcgen.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

unique_table.py

Add more mypy annotations.

2017-03-30 15:16:44 -07:00