Benjamin Bouvier b170b74b65 Fixes #600: Add a SIB byte when encoding a non-indexed load/store into r12/rsp; ...

Memory access instructions which took the GPR_ZERO_DEREF_SAFE register
class (that was removed in #600) should check for the need of either an
offset (r13/rbp) or the SIB byte (r12/rsp). Some load/store instructions
would already take an index, thus already contain the SIB byte in this
case (see instructions which have a comment telling that the else branch
already contains an SIB byte). Non-indexed memory accesses lacked the
SIB byte check, which this patch adds.

2018-11-14 13:08:54 -08:00

cranelift

Move Vim integration files into their own repo.

2018-11-13 16:13:54 -08:00

lib

Fixes #600: Add a SIB byte when encoding a non-indexed load/store into r12/rsp;

2018-11-14 13:08:54 -08:00

.travis.yml

Update to Rust 1.30.

2018-11-12 07:13:53 -08:00

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