83f21e784a
* x64: Add a smattering of lowerings for `shuffle` specializations (#5930) * x64: Add lowerings for `punpck{h,l}wd` Add some special cases for `shuffle` for more specialized x86 instructions. * x64: Add `shuffle` lowerings for `pshufd` This commit adds special-cased lowerings for the x64 `shuffle` instruction when the `pshufd` instruction alone is necessary. This is possible when the shuffle immediate permutes 32-bit values within one of the vector inputs of the `shuffle` instruction, but not both. * x64: Add shuffle lowerings for `punpck{h,l}{q,}dq` This adds specific permutations for some x86 instructions which specifically interleave high/low bytes for 32 and 64-bit values. This corresponds to the preexisting specific lowerings for interleaving 8 and 16-bit values. * x64: Add `shuffle` lowerings for `shufps` This commit adds targeted lowerings for the `shuffle` instruction that match the pattern that `shufps` supports. The `shufps` instruction selects two elements from the first vector and two elements from the second vector which means while it's not generally applicable it should still be more useful than the catch-all lowering of `shuffle`. * x64: Add shuffle support for `pshuf{l,h}w` This commit adds special lowering cases for these instructions which permute 16-bit values within a 128-bit value either within the upper or lower half of the 128-bit value. * x64: Specialize `shuffle` with an all-zeros immediate Instead of loading the all-zeros immediate from a rip-relative address at the end of the function instead generate a zero with a `pxor` instruction and then use `pshufb` to do the broadcast. * Review comments * x64: Add an AVX encoding for the `pshufd` instruction This will benefit from lack of need for alignment vs the `pshufd` instruction if working with a memory operand and additionally, as I've just learned, this reduces dependencies between instructions because the `v*` instructions zero the upper bits as opposed to preserving them which could accidentally create false dependencies in the CPU between instructions. * x64: Add more support for AVX loads/stores This commit adds VEX-encoded versions of instructions such as `mov{ss,sd,upd,ups,dqu}` for load and store operations. This also changes some signatures so the `load` helpers specifically take a `SyntheticAmode` argument which ended up doing a small refactoring of the `*_regmove` variant used for `insertlane 0` into f64x2 vectors. * x64: Enable using AVX instructions for zero regs This commit refactors the internal ISLE helpers for creating zero'd xmm registers to leverage the AVX support for all other instructions. This moves away from picking opcodes to instead picking instructions with a bit of reorganization. * x64: Remove `XmmConstOp` as an instruction All existing users can be replaced with usage of the `xmm_uninit_value` helper instruction so there's no longer any need for these otherwise constant operations. This additionally reduces manual usage of opcodes in favor of instruction helpers. * Review comments * Update test expectations
672 lines
12 KiB
Plaintext
672 lines
12 KiB
Plaintext
test compile precise-output
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set enable_simd
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target x86_64 has_avx
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function %or_from_memory(f32x4, i64) -> f32x4 {
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block0(v0: f32x4, v1: i64):
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v2 = load.f32x4 notrap aligned v1
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v3 = bor v0, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vorps %xmm0, 0(%rdi), %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vorps (%rdi), %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %copysign_from_memory(i64) -> f32 {
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block0(v0: i64):
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v1 = f32const 0.0
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v2 = load.f32 notrap aligned v0
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v3 = fcopysign v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $-2147483648, %eax
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; movd %eax, %xmm4
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; vandnps %xmm4, const(0), %xmm6
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; vandps %xmm4, 0(%rdi), %xmm8
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; vorps %xmm6, %xmm8, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movl $0x80000000, %eax
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; movd %eax, %xmm4
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; vandnps 0x1b(%rip), %xmm4, %xmm6
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; vandps (%rdi), %xmm4, %xmm8
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; vorps %xmm8, %xmm6, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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function %bor_f32x4(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vorps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vorps %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %band_not_f32x4(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = band_not v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vandnps %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vandnps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %band_not_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = band_not v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vandnpd %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vandnpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %band_not_i64x2(i64x2, i64x2) -> i64x2 {
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block0(v0: i64x2, v1: i64x2):
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v2 = band_not v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vpandn %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpandn %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f32x4_abs(f32x4) -> f32x4 {
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block0(v0: f32x4):
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v1 = fabs v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm2
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; vpcmpeqd %xmm2, %xmm2, %xmm4
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; vpsrld %xmm4, $1, %xmm6
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; vandps %xmm0, %xmm6, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpcmpeqd %xmm2, %xmm2, %xmm4
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; vpsrld $1, %xmm4, %xmm6
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; vandps %xmm6, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16x8_and(i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vpand %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpand %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f32x4_and(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vandps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vandps %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f64x2_and(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vandpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vandpd %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16x8_or(i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vpor %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpor %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f32x4_or(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vorps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vorps %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f64x2_or(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vorpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vorpd %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16x8_xor(i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vpxor %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpxor %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f32x4_xor(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vxorps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vxorps %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f64x2_xor(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vxorpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vxorpd %xmm1, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16x8_bitselect(i16x8, i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8, v2: i16x8):
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v3 = bitselect v0, v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vpand %xmm1, %xmm0, %xmm4
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; vpandn %xmm0, %xmm2, %xmm6
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; vpor %xmm6, %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; vpand %xmm0, %xmm1, %xmm4
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; vpandn %xmm2, %xmm0, %xmm6
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; vpor %xmm4, %xmm6, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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|
function %f32x4_bitselect(f32x4, f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4, v2: f32x4):
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v3 = bitselect v0, v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; vandps %xmm1, %xmm0, %xmm4
|
|
; vandnps %xmm0, %xmm2, %xmm6
|
|
; vorps %xmm6, %xmm4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vandps %xmm0, %xmm1, %xmm4
|
|
; vandnps %xmm2, %xmm0, %xmm6
|
|
; vorps %xmm4, %xmm6, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %f64x2_bitselect(f64x2, f64x2, f64x2) -> f64x2 {
|
|
block0(v0: f64x2, v1: f64x2, v2: f64x2):
|
|
v3 = bitselect v0, v1, v2
|
|
return v3
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vandpd %xmm1, %xmm0, %xmm4
|
|
; vandnpd %xmm0, %xmm2, %xmm6
|
|
; vorpd %xmm6, %xmm4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vandpd %xmm0, %xmm1, %xmm4
|
|
; vandnpd %xmm2, %xmm0, %xmm6
|
|
; vorpd %xmm4, %xmm6, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %f32x4_replace_lane(f32x4, f32) -> f32x4 {
|
|
block0(v0: f32x4, v1: f32):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vinsertps $16 %xmm0, %xmm1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vinsertps $0x10, %xmm1, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %f64x2_replace_lane(f64x2, f64) -> f64x2 {
|
|
block0(v0: f64x2, v1: f64):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vmovlhps %xmm0, %xmm1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vmovlhps %xmm1, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %i8x16_replace_lane(i8x16, i8) -> i8x16 {
|
|
block0(v0: i8x16, v1: i8):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vpinsrb $1 %xmm0, %rdi, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vpinsrb $1, %edi, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %i16x8_replace_lane(i16x8, i16) -> i16x8 {
|
|
block0(v0: i16x8, v1: i16):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vpinsrw $1 %xmm0, %rdi, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vpinsrw $1, %edi, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %i32x4_replace_lane(i32x4, i32) -> i32x4 {
|
|
block0(v0: i32x4, v1: i32):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vpinsrd $1 %xmm0, %rdi, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vpinsrd $1, %edi, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %i64x2_replace_lane(i64x2, i64) -> i64x2 {
|
|
block0(v0: i64x2, v1: i64):
|
|
v2 = insertlane v0, v1, 1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; vpinsrq $1 %xmm0, %rdi, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; vpinsrq $1, %rdi, %xmm0, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|