6b88cd44a8
* Update to rustfmt-preview. * Run "cargo fmt --all" with rustfmt 0.4.1. rustfmt 0.4.1 is the latest release of rustfmt-preview available on the stable channel. * Fix a long line that rustfmt 0.4.1 can't handle. * Remove unneeded commas left behind by rustfmt.
286 lines
10 KiB
Rust
286 lines
10 KiB
Rust
//! Instruction Set Architectures.
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//!
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//! The `isa` module provides a `TargetIsa` trait which provides the behavior specialization needed
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//! by the ISA-independent code generator. The sub-modules of this module provide definitions for
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//! the instruction sets that Cretonne can target. Each sub-module has it's own implementation of
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//! `TargetIsa`.
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//!
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//! # Constructing a `TargetIsa` instance
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//!
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//! The target ISA is built from the following information:
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//!
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//! - The name of the target ISA as a string. Cretonne is a cross-compiler, so the ISA to target
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//! can be selected dynamically. Individual ISAs can be left out when Cretonne is compiled, so a
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//! string is used to identify the proper sub-module.
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//! - Values for settings that apply to all ISAs. This is represented by a `settings::Flags`
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//! instance.
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//! - Values for ISA-specific settings.
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//!
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//! The `isa::lookup()` function is the main entry point which returns an `isa::Builder`
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//! appropriate for the requested ISA:
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//!
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//! ```
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//! use cretonne_codegen::settings::{self, Configurable};
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//! use cretonne_codegen::isa;
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//!
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//! let shared_builder = settings::builder();
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//! let shared_flags = settings::Flags::new(shared_builder);
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//!
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//! match isa::lookup("riscv") {
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//! Err(_) => {
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//! // The RISC-V target ISA is not available.
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//! }
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//! Ok(mut isa_builder) => {
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//! isa_builder.set("supports_m", "on");
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//! let isa = isa_builder.finish(shared_flags);
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//! }
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//! }
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//! ```
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//!
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//! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
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//! concurrent function compilations.
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pub use isa::constraints::{BranchRange, ConstraintKind, OperandConstraint, RecipeConstraints};
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pub use isa::encoding::{EncInfo, Encoding};
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pub use isa::registers::{regs_overlap, RegClass, RegClassIndex, RegInfo, RegUnit};
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pub use isa::stack::{StackBase, StackBaseMask, StackRef};
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use binemit;
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use flowgraph;
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use ir;
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use isa::enc_tables::Encodings;
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use regalloc;
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use result;
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use settings;
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use settings::CallConv;
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use std::boxed::Box;
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use std::fmt;
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use timing;
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#[cfg(build_riscv)]
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mod riscv;
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#[cfg(build_x86)]
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mod x86;
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#[cfg(build_arm32)]
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mod arm32;
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#[cfg(build_arm64)]
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mod arm64;
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mod constraints;
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mod enc_tables;
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mod encoding;
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pub mod registers;
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mod stack;
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/// Returns a builder that can create a corresponding `TargetIsa`
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/// or `Err(LookupError::Unsupported)` if not enabled.
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macro_rules! isa_builder {
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($module:ident, $name:ident) => {{
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#[cfg($name)]
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fn $name() -> Result<Builder, LookupError> {
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Ok($module::isa_builder())
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};
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#[cfg(not($name))]
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fn $name() -> Result<Builder, LookupError> {
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Err(LookupError::Unsupported)
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}
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$name()
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}};
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}
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/// Look for a supported ISA with the given `name`.
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/// Return a builder that can create a corresponding `TargetIsa`.
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pub fn lookup(name: &str) -> Result<Builder, LookupError> {
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match name {
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"riscv" => isa_builder!(riscv, build_riscv),
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"x86" => isa_builder!(x86, build_x86),
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"arm32" => isa_builder!(arm32, build_arm32),
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"arm64" => isa_builder!(arm64, build_arm64),
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_ => Err(LookupError::Unknown),
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}
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}
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/// Describes reason for target lookup failure
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#[derive(PartialEq, Eq, Copy, Clone, Debug)]
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pub enum LookupError {
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/// Unknown Target
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Unknown,
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/// Target known but not built and thus not supported
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Unsupported,
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}
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/// Builder for a `TargetIsa`.
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/// Modify the ISA-specific settings before creating the `TargetIsa` trait object with `finish`.
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pub struct Builder {
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setup: settings::Builder,
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constructor: fn(settings::Flags, settings::Builder) -> Box<TargetIsa>,
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}
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impl Builder {
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/// Combine the ISA-specific settings with the provided ISA-independent settings and allocate a
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/// fully configured `TargetIsa` trait object.
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pub fn finish(self, shared_flags: settings::Flags) -> Box<TargetIsa> {
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(self.constructor)(shared_flags, self.setup)
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}
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}
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impl settings::Configurable for Builder {
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fn set(&mut self, name: &str, value: &str) -> settings::Result<()> {
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self.setup.set(name, value)
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}
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fn enable(&mut self, name: &str) -> settings::Result<()> {
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self.setup.enable(name)
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}
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}
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/// After determining that an instruction doesn't have an encoding, how should we proceed to
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/// legalize it?
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///
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/// The `Encodings` iterator returns a legalization function to call.
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pub type Legalize =
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fn(ir::Inst, &mut ir::Function, &mut flowgraph::ControlFlowGraph, &TargetIsa) -> bool;
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/// Methods that are specialized to a target ISA. Implies a Display trait that shows the
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/// shared flags, as well as any isa-specific flags.
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pub trait TargetIsa: fmt::Display {
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/// Get the name of this ISA.
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fn name(&self) -> &'static str;
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/// Get the ISA-independent flags that were used to make this trait object.
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fn flags(&self) -> &settings::Flags;
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/// Does the CPU implement scalar comparisons using a CPU flags register?
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fn uses_cpu_flags(&self) -> bool {
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false
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}
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/// Does the CPU implement multi-register addressing?
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fn uses_complex_addresses(&self) -> bool {
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false
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}
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/// Get a data structure describing the registers in this ISA.
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fn register_info(&self) -> RegInfo;
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/// Returns an iterartor over legal encodings for the instruction.
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fn legal_encodings<'a>(
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&'a self,
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func: &'a ir::Function,
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inst: &'a ir::InstructionData,
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ctrl_typevar: ir::Type,
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) -> Encodings<'a>;
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/// Encode an instruction after determining it is legal.
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///
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/// If `inst` can legally be encoded in this ISA, produce the corresponding `Encoding` object.
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/// Otherwise, return `Legalize` action.
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///
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/// This is also the main entry point for determining if an instruction is legal.
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fn encode(
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&self,
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func: &ir::Function,
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inst: &ir::InstructionData,
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ctrl_typevar: ir::Type,
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) -> Result<Encoding, Legalize> {
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let mut iter = self.legal_encodings(func, inst, ctrl_typevar);
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iter.next().ok_or_else(|| iter.legalize())
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}
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/// Get a data structure describing the instruction encodings in this ISA.
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fn encoding_info(&self) -> EncInfo;
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/// Legalize a function signature.
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///
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/// This is used to legalize both the signature of the function being compiled and any called
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/// functions. The signature should be modified by adding `ArgumentLoc` annotations to all
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/// arguments and return values.
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///
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/// Arguments with types that are not supported by the ABI can be expanded into multiple
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/// arguments:
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///
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/// - Integer types that are too large to fit in a register can be broken into multiple
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/// arguments of a smaller integer type.
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/// - Floating point types can be bit-cast to an integer type of the same size, and possible
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/// broken into smaller integer types.
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/// - Vector types can be bit-cast and broken down into smaller vectors or scalars.
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///
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/// The legalizer will adapt argument and return values as necessary at all ABI boundaries.
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///
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/// When this function is called to legalize the signature of the function currently begin
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/// compiler, `current` is true. The legalized signature can then also contain special purpose
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/// arguments and return values such as:
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///
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/// - A `link` argument representing the link registers on RISC architectures that don't push
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/// the return address on the stack.
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/// - A `link` return value which will receive the value that was passed to the `link`
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/// argument.
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/// - An `sret` argument can be added if one wasn't present already. This is necessary if the
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/// signature returns more values than registers are available for returning values.
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/// - An `sret` return value can be added if the ABI requires a function to return its `sret`
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/// argument in a register.
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///
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/// Arguments and return values for the caller's frame pointer and other callee-saved registers
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/// should not be added by this function. These arguments are not added until after register
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/// allocation.
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fn legalize_signature(&self, sig: &mut ir::Signature, current: bool);
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/// Get the register class that should be used to represent an ABI argument or return value of
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/// type `ty`. This should be the top-level register class that contains the argument
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/// registers.
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///
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/// This function can assume that it will only be asked to provide register classes for types
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/// that `legalize_signature()` produces in `ArgumentLoc::Reg` entries.
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fn regclass_for_abi_type(&self, ty: ir::Type) -> RegClass;
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/// Get the set of allocatable registers that can be used when compiling `func`.
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///
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/// This set excludes reserved registers like the stack pointer and other special-purpose
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/// registers.
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fn allocatable_registers(&self, func: &ir::Function) -> regalloc::RegisterSet;
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/// Compute the stack layout and insert prologue and epilogue code into `func`.
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///
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/// Return an error if the stack frame is too large.
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fn prologue_epilogue(&self, func: &mut ir::Function) -> result::CtonResult {
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let _tt = timing::prologue_epilogue();
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// This default implementation is unlikely to be good enough.
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use ir::stackslot::{StackOffset, StackSize};
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use stack_layout::layout_stack;
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let word_size = if self.flags().is_64bit() { 8 } else { 4 };
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// Account for the SpiderMonkey standard prologue pushes.
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if func.signature.call_conv == CallConv::Baldrdash {
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let bytes = StackSize::from(self.flags().baldrdash_prologue_words()) * word_size;
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let mut ss = ir::StackSlotData::new(ir::StackSlotKind::IncomingArg, bytes);
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ss.offset = Some(-(bytes as StackOffset));
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func.stack_slots.push(ss);
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}
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layout_stack(&mut func.stack_slots, word_size)?;
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Ok(())
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}
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/// Emit binary machine code for a single instruction into the `sink` trait object.
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///
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/// Note that this will call `put*` methods on the trait object via its vtable which is not the
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/// fastest way of emitting code.
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fn emit_inst(
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&self,
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func: &ir::Function,
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inst: ir::Inst,
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divert: &mut regalloc::RegDiversions,
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sink: &mut binemit::CodeSink,
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);
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/// Emit a whole function into memory.
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///
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/// This is more performant than calling `emit_inst` for each instruction.
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fn emit_function(&self, func: &ir::Function, sink: &mut binemit::MemoryCodeSink);
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}
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