b077854b57
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
96 lines
1.3 KiB
Plaintext
96 lines
1.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %fn0(i8x8) -> i8 {
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block0(v0: i8x8):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; uminv b2, v0.8b
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; mov x4, v2.d[0]
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; subs xzr, x4, #0
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; cset x0, ne
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; ret
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function %fn1(i8x16) -> i8 {
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block0(v0: i8x16):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; uminv b2, v0.16b
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; mov x4, v2.d[0]
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; subs xzr, x4, #0
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; cset x0, ne
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; ret
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function %fn2(i16x4) -> i8 {
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block0(v0: i16x4):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; uminv h2, v0.4h
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; mov x4, v2.d[0]
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; subs xzr, x4, #0
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; cset x0, ne
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; ret
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function %fn3(i16x8) -> i8 {
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block0(v0: i16x8):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; uminv h2, v0.8h
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; mov x4, v2.d[0]
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; subs xzr, x4, #0
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; cset x0, ne
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; ret
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function %fn4(i32x2) -> i8 {
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block0(v0: i32x2):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; mov x2, v0.d[0]
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; subs xzr, xzr, x2, LSR 32
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; ccmp w2, #0, #nZcv, ne
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; cset x0, ne
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; ret
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function %fn5(i32x4) -> i8 {
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block0(v0: i32x4):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; uminv s2, v0.4s
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; mov x4, v2.d[0]
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; subs xzr, x4, #0
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; cset x0, ne
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; ret
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function %fn6(i64x2) -> i8 {
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block0(v0: i64x2):
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v1 = vall_true v0
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return v1
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}
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; block0:
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; cmeq v2.2d, v0.2d, #0
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; addp v4.2d, v2.2d, v2.2d
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; fcmp d4, d4
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; cset x0, eq
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; ret
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