a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
19 lines
303 B
Plaintext
19 lines
303 B
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %f(i64, i64) -> i64 {
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sig0 = (i64) -> i64
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block0(v0: i64, v1: i64):
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v2 = call_indirect.i64 sig0, v1(v0)
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return v2
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; blr x1
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; ldp fp, lr, [sp], #16
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; ret
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