637966dc7f
The new encoding format allows entries that mean "stop with this legalization code" which makes it possible to configure legalization actions per instruction, instead of only per controlling type variable. This patch adds the Rust side of the legalization codes: - Add an `Encodings::legalize()` method on the encoding iterator which can be called after the iterator has returned `None`. The returned code is either the default legalization action for the type, or a specific code encountered in the encoding list. - Change `lookup_enclist` to return a full iterator instead of just an offset. The two-phase lookup can bail at multiple points, each time with a default legalization code from the level 1 table. This default legalization code is stored in the returned iterator. - Change all the implementations of legal_encodings() in the ISA implementations. This change means that we don't need to return a Result any longer. The `Encodings` iterator can be empty with an associated legalization code.
108 lines
3.0 KiB
Rust
108 lines
3.0 KiB
Rust
//! ARM 32-bit Instruction Set Architecture.
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pub mod settings;
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mod abi;
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mod binemit;
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mod enc_tables;
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mod registers;
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use binemit::{CodeSink, MemoryCodeSink, emit_function};
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use super::super::settings as shared_settings;
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use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
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use isa::Builder as IsaBuilder;
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use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
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use ir;
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use regalloc;
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#[allow(dead_code)]
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struct Isa {
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shared_flags: shared_settings::Flags,
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isa_flags: settings::Flags,
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cpumode: &'static [shared_enc_tables::Level1Entry<u16>],
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}
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/// Get an ISA builder for creating ARM32 targets.
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pub fn isa_builder() -> IsaBuilder {
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IsaBuilder {
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setup: settings::builder(),
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constructor: isa_constructor,
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}
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}
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fn isa_constructor(shared_flags: shared_settings::Flags,
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builder: &shared_settings::Builder)
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-> Box<TargetIsa> {
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let level1 = if shared_flags.is_compressed() {
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&enc_tables::LEVEL1_T32[..]
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} else {
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&enc_tables::LEVEL1_A32[..]
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};
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Box::new(Isa {
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isa_flags: settings::Flags::new(&shared_flags, builder),
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shared_flags,
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cpumode: level1,
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})
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}
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impl TargetIsa for Isa {
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fn name(&self) -> &'static str {
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"arm32"
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}
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fn flags(&self) -> &shared_settings::Flags {
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&self.shared_flags
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}
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fn register_info(&self) -> RegInfo {
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registers::INFO.clone()
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}
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fn encoding_info(&self) -> EncInfo {
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enc_tables::INFO.clone()
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}
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fn legal_encodings<'a>(&'a self,
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dfg: &'a ir::DataFlowGraph,
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inst: &'a ir::InstructionData,
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ctrl_typevar: ir::Type)
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-> Encodings<'a> {
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lookup_enclist(ctrl_typevar,
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inst,
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dfg,
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self.cpumode,
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&enc_tables::LEVEL2[..],
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&enc_tables::ENCLISTS[..],
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&enc_tables::RECIPE_PREDICATES[..],
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&enc_tables::INST_PREDICATES[..],
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self.isa_flags.predicate_view())
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}
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fn legalize_signature(&self, sig: &mut ir::Signature, current: bool) {
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abi::legalize_signature(sig, &self.shared_flags, current)
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}
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fn regclass_for_abi_type(&self, ty: ir::Type) -> RegClass {
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abi::regclass_for_abi_type(ty)
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}
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fn allocatable_registers(&self, func: &ir::Function) -> regalloc::AllocatableSet {
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abi::allocatable_registers(func)
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}
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fn emit_inst(&self,
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func: &ir::Function,
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inst: ir::Inst,
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divert: &mut regalloc::RegDiversions,
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sink: &mut CodeSink) {
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binemit::emit_inst(func, inst, divert, sink)
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}
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fn emit_function(&self, func: &ir::Function, sink: &mut MemoryCodeSink) {
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emit_function(func, binemit::emit_inst, sink)
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}
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fn reloc_names(&self) -> &'static [&'static str] {
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&binemit::RELOC_NAMES
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}
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}
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