5c1b468648
* x64: Add precise-output tests for div traps
This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.
* x64: Remove conditional regalloc in `Div` instruction
Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.
* x64: Migrate non-trapping, `udiv`/`urem` to ISLE
* x64: Port checked `udiv` to ISLE
* x64: Migrate urem entirely to ISLE
* x64: Use `test` instead of `cmp` to compare-to-zero
* x64: Port `sdiv` lowering to ISLE
* x64: Port `srem` lowering to ISLE
* Tidy up regalloc behavior and fix tests
* Update docs and winch
* Review comments
* Reword again
* More refactoring test fixes
* More test fixes
22 lines
605 B
Plaintext
22 lines
605 B
Plaintext
;;! target = "x86_64"
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(module
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(func (result i64)
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(i64.const 7)
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(i64.const 5)
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(i64.rem_u)
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)
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)
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;; 0: 55 push rbp
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;; 1: 4889e5 mov rbp, rsp
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;; 4: 48c7c105000000 mov rcx, 5
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;; b: 48c7c007000000 mov rax, 7
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;; 12: 4883f900 cmp rcx, 0
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;; 16: 0f8502000000 jne 0x1e
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;; 1c: 0f0b ud2
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;; 1e: 4831d2 xor rdx, rdx
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;; 21: 48f7f1 div rcx
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;; 24: 4889d0 mov rax, rdx
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;; 27: 5d pop rbp
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;; 28: c3 ret
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