Alex Crichton 5c1b468648 x64: Migrate {s,u}{div,rem} to ISLE (#6008) ...

* x64: Add precise-output tests for div traps

This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.

* x64: Remove conditional regalloc in `Div` instruction

Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.

* x64: Migrate non-trapping, `udiv`/`urem` to ISLE

* x64: Port checked `udiv` to ISLE

* x64: Migrate urem entirely to ISLE

* x64: Use `test` instead of `cmp` to compare-to-zero

* x64: Port `sdiv` lowering to ISLE

* x64: Port `srem` lowering to ISLE

* Tidy up regalloc behavior and fix tests

* Update docs and winch

* Review comments

* Reword again

* More refactoring test fixes

* More test fixes

2023-03-14 01:44:06 +00:00

..

filetests

x64: Migrate {s,u}{div,rem} to ISLE (#6008)

2023-03-14 01:44:06 +00:00

src

winch: Refactoring wasmtime compiler integration pieces to share more between Cranelift and Winch (#5944)

2023-03-08 15:07:13 +00:00

build.rs

Making sure that new files in the winch filetests directory will cause a rebuild (#5672)

2023-01-31 19:22:11 +00:00

Cargo.toml

winch: Adding support for integration tests (#5588)

2023-01-19 07:34:48 -05:00