Files
wasmtime/meta/target/riscv
Jakob Stoklund Olesen 5a8293427d Verify that type variables have been fully bound.
The shift instructions have two type variables since the shift amount can be a
differently sized integer. Fix the RISC-V shift encodings to reflect this, and
allow i64 registers to be shifted by an i32 amount.
2016-08-04 10:21:48 -07:00
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2016-08-03 16:04:29 -07:00