8cd64e3ec6
- Panic messages must now be string literals (we used `format!()` in many places; `panic!()` can take format strings directly). - Some dead enum options with EVEX encoding stuff in old x86 backend. This will go away soon and/or be moved to the new backend anyway, so let's silence the warning for now. - A few other misc warnings.
579 lines
20 KiB
Rust
579 lines
20 KiB
Rust
//! Emitting binary x86 machine code.
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use super::enc_tables::{needs_offset, needs_sib_byte};
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use super::registers::RU;
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use crate::binemit::{bad_encoding, CodeSink, Reloc};
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use crate::ir::condcodes::{CondCode, FloatCC, IntCC};
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use crate::ir::{
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Block, Constant, ExternalName, Function, Inst, InstructionData, JumpTable, LibCall, Opcode,
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TrapCode,
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};
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use crate::isa::{RegUnit, StackBase, StackBaseMask, StackRef, TargetIsa};
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use crate::regalloc::RegDiversions;
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use cranelift_codegen_shared::isa::x86::EncodingBits;
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include!(concat!(env!("OUT_DIR"), "/binemit-x86.rs"));
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// Convert a stack base to the corresponding register.
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fn stk_base(base: StackBase) -> RegUnit {
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let ru = match base {
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StackBase::SP => RU::rsp,
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StackBase::FP => RU::rbp,
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StackBase::Zone => unimplemented!(),
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};
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ru as RegUnit
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}
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// Mandatory prefix bytes for Mp* opcodes.
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const PREFIX: [u8; 3] = [0x66, 0xf3, 0xf2];
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// Second byte for three-byte opcodes for mm=0b10 and mm=0b11.
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const OP3_BYTE2: [u8; 2] = [0x38, 0x3a];
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// A REX prefix with no bits set: 0b0100WRXB.
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const BASE_REX: u8 = 0b0100_0000;
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// Create a single-register REX prefix, setting the B bit to bit 3 of the register.
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// This is used for instructions that encode a register in the low 3 bits of the opcode and for
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// instructions that use the ModR/M `reg` field for something else.
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fn rex1(reg_b: RegUnit) -> u8 {
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let b = ((reg_b >> 3) & 1) as u8;
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BASE_REX | b
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}
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// Create a dual-register REX prefix, setting:
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//
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// REX.B = bit 3 of r/m register, or SIB base register when a SIB byte is present.
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// REX.R = bit 3 of reg register.
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fn rex2(rm: RegUnit, reg: RegUnit) -> u8 {
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let b = ((rm >> 3) & 1) as u8;
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let r = ((reg >> 3) & 1) as u8;
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BASE_REX | b | (r << 2)
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}
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// Create a three-register REX prefix, setting:
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//
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// REX.B = bit 3 of r/m register, or SIB base register when a SIB byte is present.
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// REX.R = bit 3 of reg register.
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// REX.X = bit 3 of SIB index register.
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fn rex3(rm: RegUnit, reg: RegUnit, index: RegUnit) -> u8 {
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let b = ((rm >> 3) & 1) as u8;
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let r = ((reg >> 3) & 1) as u8;
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let x = ((index >> 3) & 1) as u8;
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BASE_REX | b | (x << 1) | (r << 2)
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}
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/// Encode the RXBR' bits of the EVEX P0 byte. For an explanation of these bits, see section 2.6.1
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/// in the Intel Software Development Manual, volume 2A. These bits can be used by different
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/// addressing modes (see section 2.6.2), requiring different `vex*` functions than this one.
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fn evex2(rm: RegUnit, reg: RegUnit) -> u8 {
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let b = (!(rm >> 3) & 1) as u8;
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let x = (!(rm >> 4) & 1) as u8;
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let r = (!(reg >> 3) & 1) as u8;
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let r_ = (!(reg >> 4) & 1) as u8;
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0x00 | r_ | (b << 1) | (x << 2) | (r << 3)
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}
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/// Determines whether a REX prefix should be emitted. A REX byte always has 0100 in bits 7:4; bits
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/// 3:0 correspond to WRXB. W allows certain instructions to declare a 64-bit operand size; because
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/// [needs_rex] is only used by [infer_rex] and we prevent [infer_rex] from using [w] in
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/// [Template::build], we do not need to check again whether [w] forces an inferred REX prefix--it
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/// always does and should be encoded like `.rex().w()`. The RXB are extension of ModR/M or SIB
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/// fields; see section 2.2.1.2 in the Intel Software Development Manual.
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#[inline]
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fn needs_rex(rex: u8) -> bool {
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rex != BASE_REX
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}
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// Emit a REX prefix.
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//
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// The R, X, and B bits are computed from registers using the functions above. The W bit is
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// extracted from `bits`.
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fn rex_prefix<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(rex & 0xf8, BASE_REX);
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let w = EncodingBits::from(bits).rex_w();
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sink.put1(rex | (w << 3));
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}
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// Emit a single-byte opcode with no REX prefix.
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fn put_op1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0, "Invalid encoding bits for Op1*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Op1 encoding");
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sink.put1(bits as u8);
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}
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// Emit a single-byte opcode with REX prefix.
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fn put_rexop1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for RexOp1*");
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rex_prefix(bits, rex, sink);
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sink.put1(bits as u8);
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}
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/// Emit a single-byte opcode with inferred REX prefix.
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fn put_dynrexop1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for DynRexOp1*");
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if needs_rex(rex) {
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rex_prefix(bits, rex, sink);
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}
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode: 0F XX
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fn put_op2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0x0400, "Invalid encoding bits for Op2*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Op2 encoding");
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode: 0F XX with REX prefix.
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fn put_rexop2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0x0400, "Invalid encoding bits for RexOp2*");
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rex_prefix(bits, rex, sink);
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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/// Emit two-byte opcode: 0F XX with inferred REX prefix.
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fn put_dynrexop2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(
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bits & 0x0f00,
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0x0400,
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"Invalid encoding bits for DynRexOp2*"
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);
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if needs_rex(rex) {
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rex_prefix(bits, rex, sink);
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}
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit single-byte opcode with mandatory prefix.
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fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8c00, 0, "Invalid encoding bits for Mp1*");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp1 encoding");
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sink.put1(bits as u8);
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}
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// Emit single-byte opcode with mandatory prefix and REX.
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fn put_rexmp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0c00, 0, "Invalid encoding bits for RexMp1*");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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rex_prefix(bits, rex, sink);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode (0F XX) with mandatory prefix.
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fn put_mp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8c00, 0x0400, "Invalid encoding bits for Mp2*");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp2 encoding");
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode (0F XX) with mandatory prefix and REX.
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fn put_rexmp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0c00, 0x0400, "Invalid encoding bits for RexMp2*");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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rex_prefix(bits, rex, sink);
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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/// Emit two-byte opcode (0F XX) with mandatory prefix and inferred REX.
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fn put_dynrexmp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(
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bits & 0x0c00,
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0x0400,
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"Invalid encoding bits for DynRexMp2*"
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);
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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if needs_rex(rex) {
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rex_prefix(bits, rex, sink);
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}
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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/// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix.
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fn put_mp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8800, 0x0800, "Invalid encoding bits for Mp3*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp3 encoding");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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sink.put1(0x0f);
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sink.put1(OP3_BYTE2[(enc.mm() - 2) as usize]);
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sink.put1(bits as u8);
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}
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/// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix and REX
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fn put_rexmp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0800, 0x0800, "Invalid encoding bits for RexMp3*");
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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rex_prefix(bits, rex, sink);
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sink.put1(0x0f);
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sink.put1(OP3_BYTE2[(enc.mm() - 2) as usize]);
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sink.put1(bits as u8);
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}
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/// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix and an inferred REX prefix.
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fn put_dynrexmp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(
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bits & 0x0800,
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0x0800,
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"Invalid encoding bits for DynRexMp3*"
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);
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let enc = EncodingBits::from(bits);
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sink.put1(PREFIX[(enc.pp() - 1) as usize]);
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if needs_rex(rex) {
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rex_prefix(bits, rex, sink);
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}
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sink.put1(0x0f);
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sink.put1(OP3_BYTE2[(enc.mm() - 2) as usize]);
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sink.put1(bits as u8);
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}
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/// Defines the EVEX context for the `L'`, `L`, and `b` bits (bits 6:4 of EVEX P2 byte). Table 2-36 in
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/// section 2.6.10 (Intel Software Development Manual, volume 2A) describes how these bits can be
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/// used together for certain classes of instructions; i.e., special care should be taken to ensure
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/// that instructions use an applicable correct `EvexContext`. Table 2-39 contains cases where
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/// opcodes can result in an #UD.
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#[allow(dead_code)]
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enum EvexContext {
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RoundingRegToRegFP {
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rc: EvexRoundingControl,
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},
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NoRoundingFP {
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sae: bool,
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length: EvexVectorLength,
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},
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MemoryOp {
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broadcast: bool,
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length: EvexVectorLength,
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},
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Other {
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length: EvexVectorLength,
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},
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}
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impl EvexContext {
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/// Encode the `L'`, `L`, and `b` bits (bits 6:4 of EVEX P2 byte) for merging with the P2 byte.
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fn bits(&self) -> u8 {
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match self {
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Self::RoundingRegToRegFP { rc } => 0b001 | rc.bits() << 1,
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Self::NoRoundingFP { sae, length } => (*sae as u8) | length.bits() << 1,
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Self::MemoryOp { broadcast, length } => (*broadcast as u8) | length.bits() << 1,
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Self::Other { length } => length.bits() << 1,
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}
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}
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}
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/// The EVEX format allows choosing a vector length in the `L'` and `L` bits; see `EvexContext`.
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#[allow(dead_code)]
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enum EvexVectorLength {
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V128,
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V256,
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V512,
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}
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impl EvexVectorLength {
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/// Encode the `L'` and `L` bits for merging with the P2 byte.
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fn bits(&self) -> u8 {
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match self {
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Self::V128 => 0b00,
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Self::V256 => 0b01,
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Self::V512 => 0b10,
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// 0b11 is reserved (#UD).
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}
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}
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}
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/// The EVEX format allows defining rounding control in the `L'` and `L` bits; see `EvexContext`.
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#[allow(dead_code)]
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enum EvexRoundingControl {
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RNE,
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RD,
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RU,
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RZ,
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}
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impl EvexRoundingControl {
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/// Encode the `L'` and `L` bits for merging with the P2 byte.
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fn bits(&self) -> u8 {
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match self {
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Self::RNE => 0b00,
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Self::RD => 0b01,
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Self::RU => 0b10,
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Self::RZ => 0b11,
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}
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}
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}
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/// Defines the EVEX masking behavior; masking support is described in section 2.6.4 of the Intel
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/// Software Development Manual, volume 2A.
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#[allow(dead_code)]
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enum EvexMasking {
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None,
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Merging { k: u8 },
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Zeroing { k: u8 },
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}
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impl EvexMasking {
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/// Encode the `z` bit for merging with the P2 byte.
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fn z_bit(&self) -> u8 {
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match self {
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Self::None | Self::Merging { .. } => 0,
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Self::Zeroing { .. } => 1,
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}
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}
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/// Encode the `aaa` bits for merging with the P2 byte.
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fn aaa_bits(&self) -> u8 {
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match self {
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Self::None => 0b000,
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Self::Merging { k } | Self::Zeroing { k } => {
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debug_assert!(*k <= 7);
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*k
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}
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}
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}
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}
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/// Encode an EVEX prefix, including the instruction opcode. To match the current recipe
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/// convention, the ModR/M byte is written separately in the recipe. This EVEX encoding function
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/// only encodes the `reg` (operand 1), `vvvv` (operand 2), `rm` (operand 3) form; other forms are
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/// possible (see section 2.6.2, Intel Software Development Manual, volume 2A), requiring
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/// refactoring of this function or separate functions for each form (e.g. as for the REX prefix).
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fn put_evex<CS: CodeSink + ?Sized>(
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bits: u16,
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reg: RegUnit,
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vvvvv: RegUnit,
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rm: RegUnit,
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context: EvexContext,
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masking: EvexMasking,
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sink: &mut CS,
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) {
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let enc = EncodingBits::from(bits);
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// EVEX prefix.
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sink.put1(0x62);
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debug_assert!(enc.mm() < 0b100);
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let mut p0 = enc.mm() & 0b11;
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p0 |= evex2(rm, reg) << 4; // bits 3:2 are always unset
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sink.put1(p0);
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let mut p1 = enc.pp() | 0b100; // bit 2 is always set
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p1 |= (!(vvvvv as u8) & 0b1111) << 3;
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p1 |= (enc.rex_w() & 0b1) << 7;
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sink.put1(p1);
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let mut p2 = masking.aaa_bits();
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p2 |= (!(vvvvv as u8 >> 4) & 0b1) << 3;
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p2 |= context.bits() << 4;
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p2 |= masking.z_bit() << 7;
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sink.put1(p2);
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// Opcode
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sink.put1(enc.opcode_byte());
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// ModR/M byte placed in recipe
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}
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/// Emit a ModR/M byte for reg-reg operands.
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fn modrm_rr<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b11000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a ModR/M byte where the reg bits are part of the opcode.
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fn modrm_r_bits<CS: CodeSink + ?Sized>(rm: RegUnit, bits: u16, sink: &mut CS) {
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let reg = (bits >> 12) as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b11000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 00 ModR/M byte. This is a register-indirect addressing mode with no offset.
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/// Registers %rsp and %rbp are invalid for `rm`, %rsp indicates a SIB byte, and %rbp indicates an
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/// absolute immediate 32-bit address.
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fn modrm_rm<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b00000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 00 Mod/RM byte, with a rip-relative displacement in 64-bit mode. Effective address
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/// is calculated by adding displacement to 64-bit rip of next instruction. See intel Sw dev manual
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/// section 2.2.1.6.
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fn modrm_riprel<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_rm(0b101, reg, sink)
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}
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/// Emit a mode 01 ModR/M byte. This is a register-indirect addressing mode with 8-bit
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/// displacement.
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/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
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fn modrm_disp8<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b01000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 10 ModR/M byte. This is a register-indirect addressing mode with 32-bit
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/// displacement.
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/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
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fn modrm_disp32<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b10000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 00 ModR/M with a 100 RM indicating a SIB byte is present.
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fn modrm_sib<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_rm(0b100, reg, sink);
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}
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/// Emit a mode 01 ModR/M with a 100 RM indicating a SIB byte and 8-bit
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/// displacement are present.
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fn modrm_sib_disp8<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_disp8(0b100, reg, sink);
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}
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/// Emit a mode 10 ModR/M with a 100 RM indicating a SIB byte and 32-bit
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/// displacement are present.
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fn modrm_sib_disp32<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_disp32(0b100, reg, sink);
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}
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/// Emit a SIB byte with a base register and no scale+index.
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fn sib_noindex<CS: CodeSink + ?Sized>(base: RegUnit, sink: &mut CS) {
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let base = base as u8 & 7;
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// SIB SS_III_BBB.
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let mut b = 0b00_100_000;
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b |= base;
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sink.put1(b);
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}
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/// Emit a SIB byte with a scale, base, and index.
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fn sib<CS: CodeSink + ?Sized>(scale: u8, index: RegUnit, base: RegUnit, sink: &mut CS) {
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// SIB SS_III_BBB.
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debug_assert_eq!(scale & !0x03, 0, "Scale out of range");
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let scale = scale & 3;
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let index = index as u8 & 7;
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let base = base as u8 & 7;
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let b: u8 = (scale << 6) | (index << 3) | base;
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sink.put1(b);
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}
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/// Get the low 4 bits of an opcode for an integer condition code.
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///
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/// Add this offset to a base opcode for:
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///
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/// ---- 0x70: Short conditional branch.
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/// 0x0f 0x80: Long conditional branch.
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/// 0x0f 0x90: SetCC.
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///
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fn icc2opc(cond: IntCC) -> u16 {
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|
use crate::ir::condcodes::IntCC::*;
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match cond {
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Overflow => 0x0,
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NotOverflow => 0x1,
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UnsignedLessThan => 0x2,
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UnsignedGreaterThanOrEqual => 0x3,
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Equal => 0x4,
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NotEqual => 0x5,
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UnsignedLessThanOrEqual => 0x6,
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UnsignedGreaterThan => 0x7,
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// 0x8 = Sign.
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// 0x9 = !Sign.
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|
// 0xa = Parity even.
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|
// 0xb = Parity odd.
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|
SignedLessThan => 0xc,
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|
SignedGreaterThanOrEqual => 0xd,
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|
SignedLessThanOrEqual => 0xe,
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|
SignedGreaterThan => 0xf,
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|
}
|
|
}
|
|
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|
/// Get the low 4 bits of an opcode for a floating point condition code.
|
|
///
|
|
/// The ucomiss/ucomisd instructions set the FLAGS bits CF/PF/CF like this:
|
|
///
|
|
/// ZPC OSA
|
|
/// UN 111 000
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|
/// GT 000 000
|
|
/// LT 001 000
|
|
/// EQ 100 000
|
|
///
|
|
/// Not all floating point condition codes are supported.
|
|
fn fcc2opc(cond: FloatCC) -> u16 {
|
|
use crate::ir::condcodes::FloatCC::*;
|
|
match cond {
|
|
Ordered => 0xb, // EQ|LT|GT => *np (P=0)
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|
Unordered => 0xa, // UN => *p (P=1)
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|
OrderedNotEqual => 0x5, // LT|GT => *ne (Z=0),
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|
UnorderedOrEqual => 0x4, // UN|EQ => *e (Z=1)
|
|
GreaterThan => 0x7, // GT => *a (C=0&Z=0)
|
|
GreaterThanOrEqual => 0x3, // GT|EQ => *ae (C=0)
|
|
UnorderedOrLessThan => 0x2, // UN|LT => *b (C=1)
|
|
UnorderedOrLessThanOrEqual => 0x6, // UN|LT|EQ => *be (Z=1|C=1)
|
|
Equal | // EQ
|
|
NotEqual | // UN|LT|GT
|
|
LessThan | // LT
|
|
LessThanOrEqual | // LT|EQ
|
|
UnorderedOrGreaterThan | // UN|GT
|
|
UnorderedOrGreaterThanOrEqual // UN|GT|EQ
|
|
=> panic!("{} not supported", cond),
|
|
}
|
|
}
|
|
|
|
/// Emit a single-byte branch displacement to `destination`.
|
|
fn disp1<CS: CodeSink + ?Sized>(destination: Block, func: &Function, sink: &mut CS) {
|
|
let delta = func.offsets[destination].wrapping_sub(sink.offset() + 1);
|
|
sink.put1(delta as u8);
|
|
}
|
|
|
|
/// Emit a four-byte branch displacement to `destination`.
|
|
fn disp4<CS: CodeSink + ?Sized>(destination: Block, func: &Function, sink: &mut CS) {
|
|
let delta = func.offsets[destination].wrapping_sub(sink.offset() + 4);
|
|
sink.put4(delta);
|
|
}
|
|
|
|
/// Emit a four-byte displacement to jump table `jt`.
|
|
fn jt_disp4<CS: CodeSink + ?Sized>(jt: JumpTable, func: &Function, sink: &mut CS) {
|
|
let delta = func.jt_offsets[jt].wrapping_sub(sink.offset() + 4);
|
|
sink.put4(delta);
|
|
sink.reloc_jt(Reloc::X86PCRelRodata4, jt);
|
|
}
|
|
|
|
/// Emit a four-byte displacement to `constant`.
|
|
fn const_disp4<CS: CodeSink + ?Sized>(constant: Constant, func: &Function, sink: &mut CS) {
|
|
let offset = func.dfg.constants.get_offset(constant);
|
|
let delta = offset.wrapping_sub(sink.offset() + 4);
|
|
sink.put4(delta);
|
|
sink.reloc_constant(Reloc::X86PCRelRodata4, offset);
|
|
}
|