32a7593c94
Remove the boolean types from cranelift, and the associated instructions breduce, bextend, bconst, and bint. Standardize on using 1/0 for the return value from instructions that produce scalar boolean results, and -1/0 for boolean vector elements. Fixes #3205 Co-authored-by: Afonso Bordado <afonso360@users.noreply.github.com> Co-authored-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Co-authored-by: Chris Fallin <chris@cfallin.org>
134 lines
5.0 KiB
Plaintext
134 lines
5.0 KiB
Plaintext
test interpret
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test run
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target x86_64
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target aarch64
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target s390x
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target riscv64
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function %fsub_f32(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fsub v0, v1
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return v2
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}
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; run: %fsub_f32(0x0.5, 0x1.0) == -0x1.6p-1
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; run: %fsub_f32(0x1.5, 0x2.9) == -0x1.4p0
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; run: %fsub_f32(0x1.1p10, 0x1.4p1) == 0x1.0f6p10
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; run: %fsub_f32(0x1.4cccccp0, 0x1.8p0) == -0x1.9999a0p-3
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; run: %fsub_f32(0x1.b33334p0, 0x1.99999ap-2) == 0x1.4ccccep0
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; run: %fsub_f32(0x1.333334p-1, 0x1.666666p1) == -0x1.199998p1
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; run: %fsub_f32(-0x0.5, -0x1.0) == 0x1.6p-1
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; run: %fsub_f32(-0x1.5, -0x2.9) == 0x1.4p0
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; run: %fsub_f32(-0x1.1p10, -0x1.333334p-1) == -0x1.0fd99ap10
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; run: %fsub_f32(-0x1.99999ap-2, -0x1.4cccccp0) == 0x1.ccccccp-1
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; run: %fsub_f32(-0x1.8p0, -0x1.b33334p0) == 0x1.9999a0p-3
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; run: %fsub_f32(-0x1.4p1, -0x1.666666p1) == 0x1.333330p-2
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; run: %fsub_f32(0x0.5, -0x1.0) == 0x1.5p0
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; run: %fsub_f32(0x1.b33334p0, -0x1.b33334p0) == 0x1.b33334p1
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; Specials
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; run: %fsub_f32(0x0.0, -0x0.0) == 0x0.0
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; run: %fsub_f32(-0x0.0, 0x0.0) == -0x0.0
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; run: %fsub_f32(-0x0.0, +Inf) == -Inf
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; run: %fsub_f32(0x0.0, -Inf) == +Inf
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; run: %fsub_f32(+Inf, -Inf) == +Inf
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; run: %fsub_f32(-Inf, +Inf) == -Inf
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; F32 Epsilon / Max / Min Positive
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; run: %fsub_f32(0x1.0p-23, 0x1.fffffep127) == -0x1.fffffep127
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; run: %fsub_f32(0x1.0p-23, 0x1.0p-126) == 0x1.0p-23
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; run: %fsub_f32(0x1.fffffep127, 0x1.fffffep127) == 0x0.0
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; run: %fsub_f32(0x1.0p-126, 0x1.fffffep127) == -0x1.fffffep127
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; run: %fsub_f32(0x1.0p-126, 0x1.0p-126) == 0x0.0
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; F32 Subnormals
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; run: %fsub_f32(0x0.8p-126, -0x0.800002p-126) == 0x1.000002p-126
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; run: %fsub_f32(0x0.8p-126, 0x1.0) == -0x1.0
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; run: %fsub_f32(-0x0.800002p-126, 0x1.0) == -0x1.0
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; F32 NaN's
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; For NaN's this operation is specified as producing a value that is a NaN
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function %fsub_is_nan_f32(f32, f32) -> i32 {
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block0(v0: f32, v1: f32):
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v2 = fsub v0, v1
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v3 = fcmp ne v2, v2
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v4 = uextend.i32 v3
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return v4
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}
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; run: %fsub_is_nan_f32(0x0.0, +NaN) == 1
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; run: %fsub_is_nan_f32(0x0.0, -NaN) == 1
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; run: %fsub_is_nan_f32(0x0.0, +NaN:0x0) == 1
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; run: %fsub_is_nan_f32(0x0.0, +NaN:0x1) == 1
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; run: %fsub_is_nan_f32(0x0.0, +NaN:0x300001) == 1
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; run: %fsub_is_nan_f32(0x0.0, -NaN:0x0) == 1
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; run: %fsub_is_nan_f32(0x0.0, -NaN:0x1) == 1
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; run: %fsub_is_nan_f32(0x0.0, -NaN:0x300001) == 1
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; run: %fsub_is_nan_f32(0x0.0, +sNaN:0x1) == 1
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; run: %fsub_is_nan_f32(0x0.0, -sNaN:0x1) == 1
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; run: %fsub_is_nan_f32(0x0.0, +sNaN:0x200001) == 1
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; run: %fsub_is_nan_f32(0x0.0, -sNaN:0x200001) == 1
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function %fsub_f64(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fsub v0, v1
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return v2
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}
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; run: %fsub_f64(0x0.5, 0x1.0) == -0x1.6p-1
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; run: %fsub_f64(0x1.5, 0x2.9) == -0x1.4
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; run: %fsub_f64(0x1.1p10, 0x1.4p1) == 0x1.0f6p10
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; run: %fsub_f64(0x1.4cccccccccccdp0, 0x1.8p0) == -0x1.9999999999998p-3
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; run: %fsub_f64(0x1.b333333333333p0, 0x1.999999999999ap-2) == 0x1.4ccccccccccccp0
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; run: %fsub_f64(0x1.3333333333333p-1, 0x1.6666666666666p1) == -0x1.1999999999999p1
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; run: %fsub_f64(-0x0.5, -0x1.0) == 0x1.6p-1
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; run: %fsub_f64(-0x1.5, -0x2.9) == 0x1.4
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; run: %fsub_f64(-0x1.1p10, -0x1.3333333333333p-1) == -0x1.0fd999999999ap10
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; run: %fsub_f64(-0x1.999999999999ap-2, -0x1.4cccccccccccdp0) == 0x1.ccccccccccccdp-1
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; run: %fsub_f64(-0x1.8p0, -0x1.b333333333333p0) == 0x1.9999999999998p-3
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; run: %fsub_f64(-0x1.4p1, -0x1.6666666666666p1) == 0x1.3333333333330p-2
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; run: %fsub_f64(0x0.5, -0x1.0) == 0x1.5
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; run: %fsub_f64(0x1.b333333333333p0, -0x1.b333333333333p0) == 0x1.b333333333333p1
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; Specials
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; run: %fsub_f64(0x0.0, -0x0.0) == 0x0.0
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; run: %fsub_f64(-0x0.0, 0x0.0) == -0x0.0
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; run: %fsub_f64(-0x0.0, +Inf) == -Inf
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; run: %fsub_f64(0x0.0, -Inf) == +Inf
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; run: %fsub_f64(+Inf, -Inf) == +Inf
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; run: %fsub_f64(-Inf, +Inf) == -Inf
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; F64 Epsilon / Max / Min Positive
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; run: %fsub_f64(0x1.0p-52, 0x1.fffffffffffffp1023) == -0x1.fffffffffffffp1023
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; run: %fsub_f64(0x1.0p-52, 0x1.0p-1022) == 0x1.0p-52
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; run: %fsub_f64(0x1.fffffffffffffp1023, 0x1.fffffffffffffp1023) == 0x0.0
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; run: %fsub_f64(0x1.0p-1022, 0x1.fffffffffffffp1023) == -0x1.fffffffffffffp1023
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; run: %fsub_f64(0x1.0p-1022, 0x1.0p-1022) == 0x0.0
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; F64 Subnormals
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; run: %fsub_f64(0x0.8p-1022, -0x0.8p-1022) == 0x1.0000000000000p-1022
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; run: %fsub_f64(0x0.8p-1022, 0x1.0) == -0x1.0
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; run: %fsub_f64(-0x0.8p-1022, 0x1.0) == -0x1.0
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; F64 NaN's
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; For NaN's this operation is specified as producing a value that is a NaN
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function %fsub_is_nan_f64(f64, f64) -> i32 {
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block0(v0: f64, v1: f64):
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v2 = fsub v0, v1
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v3 = fcmp ne v2, v2
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v4 = uextend.i32 v3
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return v4
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}
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; run: %fsub_is_nan_f64(0x0.0, +NaN) == 1
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; run: %fsub_is_nan_f64(0x0.0, -NaN) == 1
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; run: %fsub_is_nan_f64(0x0.0, +NaN:0x0) == 1
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; run: %fsub_is_nan_f64(0x0.0, +NaN:0x1) == 1
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; run: %fsub_is_nan_f64(0x0.0, +NaN:0x4000000000001) == 1
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; run: %fsub_is_nan_f64(0x0.0, -NaN:0x0) == 1
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; run: %fsub_is_nan_f64(0x0.0, -NaN:0x1) == 1
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; run: %fsub_is_nan_f64(0x0.0, -NaN:0x4000000000001) == 1
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; run: %fsub_is_nan_f64(0x0.0, +sNaN:0x1) == 1
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; run: %fsub_is_nan_f64(0x0.0, -sNaN:0x1) == 1
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; run: %fsub_is_nan_f64(0x0.0, +sNaN:0x4000000000001) == 1
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; run: %fsub_is_nan_f64(0x0.0, -sNaN:0x4000000000001) == 1
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