34146435e5
Also make sure we generate type checks for the controlling type variable in legalization patterns. This is not needed for encodings since the encoding tables are already keyed on the controlling type variable.
102 lines
2.8 KiB
Python
102 lines
2.8 KiB
Python
"""
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Custom legalization patterns for Intel.
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"""
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from __future__ import absolute_import
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from cdsl.ast import Var
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from cdsl.xform import Rtl, XFormGroup
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from base.immediates import imm64, floatcc
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from base.types import i32, i64
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from base import legalize as shared
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from base import instructions as insts
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from . import instructions as x86
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from .defs import ISA
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intel_expand = XFormGroup(
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'intel_expand',
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"""
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Legalize instructions by expansion.
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Use Intel-specific instructions if needed.
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""",
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isa=ISA, chain=shared.expand)
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a = Var('a')
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dead = Var('dead')
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x = Var('x')
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xhi = Var('xhi')
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y = Var('y')
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a1 = Var('a1')
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a2 = Var('a2')
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#
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# Division and remainder.
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#
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intel_expand.legalize(
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a << insts.udiv(x, y),
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Rtl(
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xhi << insts.iconst(imm64(0)),
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(a, dead) << x86.udivmodx(x, xhi, y)
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))
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intel_expand.legalize(
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a << insts.urem(x, y),
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Rtl(
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xhi << insts.iconst(imm64(0)),
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(dead, a) << x86.udivmodx(x, xhi, y)
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))
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for ty in [i32, i64]:
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intel_expand.legalize(
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a << insts.sdiv.bind(ty)(x, y),
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Rtl(
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xhi << insts.sshr_imm(x, imm64(ty.lane_bits() - 1)),
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(a, dead) << x86.sdivmodx(x, xhi, y)
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))
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intel_expand.legalize(
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a << insts.srem.bind(ty)(x, y),
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Rtl(
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xhi << insts.sshr_imm(x, imm64(ty.lane_bits() - 1)),
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(dead, a) << x86.sdivmodx(x, xhi, y)
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))
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# Floating point condition codes.
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#
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# The 8 condition codes in `supported_floatccs` are directly supported by a
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# `ucomiss` or `ucomisd` instruction. The remaining codes need legalization
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# patterns.
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# Equality needs an explicit `ord` test which checks the parity bit.
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intel_expand.legalize(
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a << insts.fcmp(floatcc.eq, x, y),
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Rtl(
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a1 << insts.fcmp(floatcc.ord, x, y),
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a2 << insts.fcmp(floatcc.ueq, x, y),
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a << insts.band(a1, a2)
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))
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intel_expand.legalize(
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a << insts.fcmp(floatcc.ne, x, y),
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Rtl(
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a1 << insts.fcmp(floatcc.uno, x, y),
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a2 << insts.fcmp(floatcc.one, x, y),
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a << insts.bor(a1, a2)
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))
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# Inequalities that need to be reversed.
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for cc, rev_cc in [
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(floatcc.lt, floatcc.gt),
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(floatcc.le, floatcc.ge),
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(floatcc.ugt, floatcc.ult),
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(floatcc.uge, floatcc.ule)]:
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intel_expand.legalize(
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a << insts.fcmp(cc, x, y),
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Rtl(
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a << insts.fcmp(rev_cc, y, x)
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))
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# We need to modify the CFG for min/max legalization.
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intel_expand.custom_legalize(insts.fmin, 'expand_minmax')
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intel_expand.custom_legalize(insts.fmax, 'expand_minmax')
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# Conversions from unsigned need special handling.
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intel_expand.custom_legalize(insts.fcvt_from_uint, 'expand_fcvt_from_uint')
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