1dddba649a
The x64 backend currently builds the `RealRegUniverse` in a way that is generating somewhat suboptimal code. In many blocks, we see uses of callee-save (non-volatile) registers (r12, r13, r14, rbx) first, even in very short leaf functions where there are plenty of volatiles to use. This is leading to unnecessary spills/reloads. On one (local) test program, a medium-sized C benchmark compiled to Wasm and run on Wasmtime, I am seeing a ~10% performance improvement with this change; it will be less pronounced in programs with high register pressure (there we are likely to use all registers regardless, so the prologue/epilogue will save/restore all callee-saves), or in programs with fewer calls, but this is a clear win for small functions and in many cases removes prologue/epilogue clobber-saves altogether. Separately, I think the RA's coalescing is tripping up a bit in some cases; see e.g. the filetest touched by this commit that loads a value into %rsi then moves to %rax and returns immediately. This is an orthogonal issue, though, and should be addressed (if worthwhile) in regalloc.rs.
94 lines
2.2 KiB
Plaintext
94 lines
2.2 KiB
Plaintext
test compile
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set enable_simd
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target x86_64 has_ssse3 has_sse41
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feature "experimental_x64"
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;; shuffle
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function %shuffle_different_ssa_values() -> i8x16 {
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block0:
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v0 = vconst.i8x16 0x00
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v1 = vconst.i8x16 0x01
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v2 = shuffle v0, v1, 0x11000000000000000000000000000000 ; pick the second lane of v1, the rest use the first lane of v0
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return v2
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}
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; check: load_const VCodeConstant(3), %xmm1
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; nextln: load_const VCodeConstant(2), %xmm0
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; nextln: load_const VCodeConstant(0), %xmm2
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; nextln: pshufb %xmm2, %xmm1
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; nextln: load_const VCodeConstant(1), %xmm2
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; nextln: pshufb %xmm2, %xmm0
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; nextln: orps %xmm1, %xmm0
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function %shuffle_same_ssa_value() -> i8x16 {
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block0:
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v1 = vconst.i8x16 0x01
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v2 = shuffle v1, v1, 0x13000000000000000000000000000000 ; pick the fourth lane of v1 and the rest from the first lane of v1
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return v2
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}
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; check: load_const VCodeConstant(1), %xmm0
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; nextln: load_const VCodeConstant(0), %xmm1
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; nextln: pshufb %xmm1, %xmm0
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;; swizzle
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function %swizzle() -> i8x16 {
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block0:
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v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = swizzle.i8x16 v0, v1
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return v2
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}
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; check: load_const VCodeConstant(1), %xmm1
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; nextln: load_const VCodeConstant(1), %xmm0
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; nextln: load_const VCodeConstant(0), %xmm2
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; nextln: paddusb %xmm2, %xmm0
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; nextln: pshufb %xmm0, %xmm1
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; nextln: movdqa %xmm1, %xmm0
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;; splat
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function %splat_i8(i8) -> i8x16 {
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block0(v0: i8):
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v1 = splat.i8x16 v0
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return v1
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}
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; check: uninit %xmm0
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; nextln: pinsrb $$0, %rdi, %xmm0
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; nextln: pxor %xmm1, %xmm1
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; nextln: pshufb %xmm1, %xmm0
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function %splat_b16() -> b16x8 {
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block0:
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v0 = bconst.b16 true
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v1 = splat.b16x8 v0
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return v1
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}
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; check: uninit %xmm0
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; nextln: pinsrw $$0, %rsi, %xmm0
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; nextln: pinsrw $$1, %rsi, %xmm0
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; nextln: pshufd $$0, %xmm0, %xmm0
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function %splat_i32(i32) -> i32x4 {
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block0(v0: i32):
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v1 = splat.i32x4 v0
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return v1
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}
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; check: uninit %xmm0
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; nextln: pinsrd $$0, %rdi, %xmm0
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; nextln: pshufd $$0, %xmm0, %xmm0
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function %splat_f64(f64) -> f64x2 {
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block0(v0: f64):
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v1 = splat.f64x2 v0
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return v1
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}
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; check: uninit %xmm1
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; nextln: movsd %xmm0, %xmm1
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; nextln: movlhps %xmm0, %xmm1
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