86 lines
3.2 KiB
Markdown
86 lines
3.2 KiB
Markdown
# June 6 project call
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**See the [instructions](../README.md) for details on how to attend**
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## Agenda
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1. Opening, welcome and roll call
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1. Note: meeting notes linked in the invite.
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1. Please help add your name to the meeting notes.
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1. Please help take notes.
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1. Thanks!
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1. Announcements
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1. _Submit a PR to add your announcement here_
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1. Other agenda items
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1. _Submit a PR to add your item here_
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## Notes
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### Attendees
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- abrown
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- akirilov
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- avanhattum
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- cfallin
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- fitzgen
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- sparkerhaynes
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### Notes
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- ISLE porting status and plans?
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- abrown: Quarterly goals at Intel, port a number of instructions over to ISLE.
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- Want to continue doing so.
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- Issue is that all the hard ones are left.
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- We need more people to look at it.
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- akirilov: Quarterly basis too.
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- Our approach was different, we've gone for the harder ones first.
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- Trying to improve test coverage.
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- abrown: How are you guys tracking coverage?
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- akirilov: It's just manual, the bar is currently quite low so easy to see where they're missing.
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- Interpreter has failed to handle some cases, something to do with splat.
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- Some run tests don't check the return values.
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- Sometimes disabling the interpreter tests.
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- cfallin: Sounds like the right approach.
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- abrown: What's the state of SIMD interpreter support? afonso was working on it.
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- cfallin: Don't know what happened to afonso, work has stalled on it.
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- akirilov: Regalloc2 limitation of only 2 reg classes
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- SVE will need a predicate file, same for AVX-512.
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- cfallin: Bit packing issue, could remove the 'mod' operands and reuse that bit.
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- akirilov: Will four classes be enough..? It is probably fine for AArch64.
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- cfallin: Will keep this on my back burner.
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# standups
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- fitzgen: No updates.
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- avanhattum: Better semantics for verification.
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- SAIL for x64 and arm.
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- Figuring out what work is needed to use modern SAIL for x64.
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- Working on shim code to avoid annoting machine instructions.
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- akirilov: cranelift CFI patch updates and Fiber changes for MacOS.
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- bjorn3 gave feedback and noticed codegen wasn't right.
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- some branches were elided and the branch target instructions ended up as the last instruction, not first.
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- pointer authentication is still disabled in qemu.
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- cfallin: Implemented alias analysis for load elimination, with okay speedups.
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- could have benefitted some option optimizations, such as GVN
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- So developing a unified framework for rewrite rules in the mid-end.
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- egraphs seem the right approach.
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- need an adapter to convert the egraph to LowerCtx: clif -> egraph -> vcode
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- Then need to figure out isle rewrite rules.
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- Framework will subsume all the existing mid-end optimisations.
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- Also worked on a fix regalloc2 issue, reducing stack size usage.
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- alexa: static rewrite rules or equality saturation?
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- chris: equality.
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- abrown: shared memory in wasmtime.
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- impacts cranelift through `memory_size` instruction.
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- How are we gonna test this? Looking for ideas and feedback.
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- Ported some atomic operations for x64, not sure CAS is right.
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- sparker: Dynamic vector RFC is up in code form.
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- It's a bit rough and would greatly appreciate some feedback.
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- cfallin: does qemu support sve?
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- sparker: yes.
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