Trevor Elliott d54a27d0ea Allocate temporary intermediates when loading constants on aarch64 (#5366) ...

As loading constants on aarch64 can take up to 4 instructions, we need to plumb through some additional registers. Rather than pass a fixed list of registers in, pass an allocation function.

2022-12-01 22:29:36 +00:00

..

abi.rs

Allocate temporary intermediates when loading constants on aarch64 (#5366)

2022-12-01 22:29:36 +00:00

blockorder.rs

Initial forward-edge CFI implementation (#3693)

2022-09-08 09:35:58 -05:00

buffer.rs

Implement AOT compilation for components (#5160)

2022-11-02 15:26:26 +00:00

compile.rs

Cranelift: log number of CLIF insts/blocks to optimize/lower (#5333)

2022-11-28 19:35:29 +00:00

helpers.rs

cranelift: Remove booleans (#5031)

2022-10-17 16:00:27 -07:00

inst_common.rs

Port branches to ISLE (AArch64) (#4943)

2022-09-26 09:45:32 +01:00

isle.rs

Remove sig data arg and ret fields to reduce size (#5319)

2022-11-30 07:19:41 -08:00

lower.rs

Bump regalloc2 to 0.5.0 (#5345)

2022-11-29 11:25:35 -08:00

mod.rs

cranelift: Fix implicit pointer argument register use (#5301)

2022-11-18 16:47:03 -08:00

reg.rs

Bump regalloc2 to 0.5.0 (#5345)

2022-11-29 11:25:35 -08:00

valueregs.rs

Switch Cranelift over to regalloc2. (#3989)

2022-04-14 10:28:21 -07:00

vcode.rs

Cranelift: add debug logs counting how many vcode instructions and blocks we lower to (#5332)

2022-11-28 18:57:02 +00:00