Commit Graph

4316 Commits

Author SHA1 Message Date
Nick Fitzgerald
253e28ca4f Cranelift: Rewrite (x>>k)<<k into masking off the bottom k bits (#5673)
* Cranelift: Rewrite `(x>>k)<<k` into masking off the bottom `k` bits

* Add a runtest for exercising our rewrite of `(x >> k) << k` into masking
2023-01-31 21:11:12 +00:00
Alex Crichton
7f2c8e6344 Fix some warnings on nightly Rust (#5668)
* Fix some warnings on nightly Rust

Cargo is warning about the usage of workspace dependencies where the
workspace declaration does not mention `default-features` but the
dependency mentions `default-features`, so this explicitly turns off
default features for `cranelift-codegen` at the workspace level and
removes the explicit `default-features = false` at the manifest levels.

* Explicitly enable default feature in wasmtime

* Enable another feature
2023-01-31 20:54:58 +00:00
Nick Fitzgerald
7aa240e0f2 Cranelift: constant propagate shifts (#5671)
Thanks to Souper for pointing out we weren't doing this!
2023-01-31 12:06:53 -08:00
Trevor Elliott
10fcd14287 Remove unused code from the write module (#5674)
The DisplayValuesWithDelimiter struct is no longer used.
2023-01-31 19:45:59 +00:00
Nick Fitzgerald
c9d1c068bc Cranelift: Add egraph rule to rewrite x * C ==> x << log2(C) when C is a power of two (#5647) 2023-01-31 18:04:17 +00:00
Jamey Sharp
61270cdaed ISLE: reject multi-term rules with explicit priorities (#5663)
In multi-terms, all matching rules fire. We treat the result as an
unordered set of values, so setting rule priorities is meaningless. We
want to prohibit relying on the rule match order in this case.

Also, codegen can produce invalid Rust if rules with different
priorities both match against a multi-term. We first documented this
symptom in #5647. As far as I can figure, prohibiting rule priorities
prevents all possible instances of that bug.

At some point in the future we might decide we want to carefully define
semantics for multi-term result ordering, at which point we can revisit
this.
2023-01-31 09:08:31 -08:00
Nick Fitzgerald
bf4d0e9212 Cranelift: Fix select condition harvesting (#5662)
Souper requires an `i1` condition value, we don't and will implicitly check
against 0. We were truncating conditions but should actually be doing the
comparison against `0`.
2023-01-30 21:25:14 -08:00
Trevor Elliott
b5692db7ce Remove boolean parameters from instruction builder functions (#5658)
Remove the boolean parameters from the instruction builder functions, as they were only ever used with true. Additionally, change the returns and branches functions to imply terminates_block.
2023-01-30 16:12:05 -08:00
Nick Fitzgerald
e4fa355866 cranelift: Generate the correct souper size for comparisons in LHSes (#5659) 2023-01-30 15:32:47 -08:00
Nick Fitzgerald
ffcd61b520 Cranelift: Harvest each Souper LHS into its own file (#5649)
* Cranelift: Harvest each Souper LHS into its own file

Souper only handles one input LHS at a time, so this makes it way easier to
script. Don't need to try and parse each LHS.

* Add audit of `arrayref` version 0.3.6

* Add audit of `constant_time_eq` version 0.2.4
2023-01-30 13:24:11 -08:00
Trevor Elliott
a5698cedf8 cranelift: Remove brz and brnz (#5630)
Remove the brz and brnz instructions, as their behavior is now redundant with brif.
2023-01-30 20:34:56 +00:00
yuyang
77cf547f41 fix issue 5569. (#5612)
* add regression test file.

* fix issute5569.

* enable code length check.
2023-01-30 10:01:33 -08:00
Trevor Elliott
20a216923b Fix an assertion failure with an empty Switch (#5650)
Fix an error introduced in #5644, where an unsigned subtraction from zero was possible with an empty Switch structure. Additionally, missing the empty case caused us to not emit a branch to the default block. This PR fixes the issue by detecting the empty Switch case early, and emitting a jump.
2023-01-28 01:46:11 +00:00
Nick Fitzgerald
ffbcc67eb3 Cranelift: Consider shifts as "simple" arithmetic in egraph cost model (#5646) 2023-01-27 16:30:42 -08:00
Trevor Elliott
b47006d432 Rework the switch module in cranelift-frontend in terms of brif (#5644)
Rework the compilation strategy for switch to:
* use brif instead of brz and brnz
* generate tables inline, rather than delyaing them to after the decision tree has been generated
* avoid allocating new vectors by using slices into the sorted contiguous ranges
* avoid generating some unconditional jumps
* output differences in test output using the similar crate for easier debugging
2023-01-27 16:00:40 -08:00
Saúl Cabrera
0f8393508a cranelift-codegen: Expose EmitState and EmitInfo from aarch64 (#5640)
This commit exposes `EmitState` and `EmitInfo` so that they can be consumed by
Winch.

This is a follow up to https://github.com/bytecodealliance/wasmtime/pull/5570,
in which this should've been included.
2023-01-27 19:36:26 +00:00
Trevor Elliott
058d93bc64 Migrate cranelift-wasm to brif (#5638)
Incrementally working towards removing brz and brnz completely.
2023-01-27 10:34:41 -08:00
Jamey Sharp
915801551b Delete old cranelift-preopt crate (#5642)
Most of these optimizations are in the egraph `cprop.isle` rules now,
making a separate crate unnecessary.

Also I think the `udiv` optimizations here are straight-up wrong (doing
signed instead of unsigned division, and panicking instead of preserving
traps on division by zero) so I'm guessing this crate isn't seriously
used anywhere.

At the least, bjorn3 confirms that cg_clif doesn't use this, and I've
verified that Wasmtime doesn't either.

Closes #1090.
2023-01-26 21:32:33 +00:00
Trevor Elliott
a181ad2932 Cleanup the use of maybe_uextend in the x64 lowerings (#5637)
Use maybe_uextend for the brnz lowerings on x64.
2023-01-25 17:28:48 -08:00
Trevor Elliott
7926808e8e riscv64: improve unordered comparison generated code (#5636)
Improve the generated code for unordered floating point comparisons by negating the comparison and inveritng the branches. This allows us to pick the unordered versions, which generate significantly better code.
2023-01-25 17:28:28 -08:00
Alex Crichton
a7d0d00e57 Update wasm-tools crates (#5631)
Nothing major pulled in here, but wanted to update to the latest
versions which enable tail calls by default. When used in Wasmtime,
however, the feature is disabled without the possibility of being
enabled since it's not implemented.
2023-01-25 16:33:26 +00:00
Trevor Elliott
b58a197d33 cranelift: Add a conditional branch instruction with two targets (#5446)
Add a conditional branch instruction with two targets: brif. This instruction will eventually replace brz and brnz, as it encompasses the behavior of both.

This PR also changes the InstructionData layout for instruction formats that hold BlockCall values, taking the same approach we use for Value arguments. This allows branch_destination to return a slice to the BlockCall values held in the instruction, rather than requiring that we pattern match on InstructionData to fetch the then/else blocks.

Function generation for fuzzing has been updated to generate uses of brif, and I've run the cranelift-fuzzgen target locally for hours without triggering any new failures.
2023-01-24 14:37:16 -08:00
bjorn3
ec6922ff24 Produce an error at runtime rather than at compile time for unsupported architectures in cranelift-native (#5627) 2023-01-24 19:17:28 +00:00
Jamey Sharp
bfc6aad184 cranelift-isle: codegen from new IR (#5435)
ISLE's existing code-generation strategy doesn't generate the most
efficient matching order for rules. This PR completely replaces it.

With this PR applied, wasmtime compile retires 2% fewer instructions on
the pulldown-cmark and spidermonkey benchmarks from Sightglass.

A dev build of cranelift-codegen from an empty target/ directory takes
2% less time. The build script, invoking ISLE, takes a little longer,
but Rust can compile the generated code faster, so it balances out.
2023-01-23 12:27:51 -08:00
Jamey Sharp
fef9f64d2c x86: Test paired udiv/urem (#5573)
Ideally these pairs of CLIF instructions should emit a single x86
instruction, but they don't today. This test will tell us if somebody
fixes that.

Similar tests might make sense for imul/umulhi as well as signed
versions, but I haven't tried that.
2023-01-23 11:44:27 -08:00
Afonso Bordado
ae441c50b6 fuzzgen: Reenable some RISCV instructions (#5615) 2023-01-23 09:03:07 -08:00
Saúl Cabrera
0e6e802c34 docs: Fix typo (#5620) 2023-01-23 09:05:33 -06:00
yuyang
7e10bd1f58 fix issue #5497 #5524 #5526. (#5595)
* fix issue 5497.

* fix issue 5524

* fix issue 5497 5524 5526.

* some clif change because of reg alloc.
2023-01-20 14:06:26 -08:00
yuyang
299b8187f8 fix issue 5525. (#5603)
* fix issue 5525.

* reg alloc changed.
2023-01-20 09:53:54 -08:00
Chris Fallin
1faff8c2ce Enable egraph-based optimization by default. (#5587)
This PR follows up on #5382 and #5391, which rebuilt the egraph-based optimization framework to be more performant, by enabling it by default.

Based on performance results in #5382 (my measurements on SpiderMonkey and bjorn3's independent confirmation with cg_clif), it seems that this is reasonable to enable. Now that we have been fuzzing compiler configurations with egraph opts (#5388) for 6 weeks, having fixed a few fuzzbugs that came up (#5409, #5420, #5438) and subsequently received no further reports from OSS-Fuzz, I believe it is stable enough to rely on.

This PR enables `use_egraphs`, and also normalizes its meaning: previously it forced optimization (it basically meant "turn on the egraph optimization machinery"), now it runs egraph opts if the opt level indicates (it means "use egraphs to optimize if we are going to optimize"). The conditionals in the top-level pass driver are a little subtle, but will get simpler once we can remove the non-egraph path (which we plan to do eventually!).

Fixes #5181.
2023-01-19 15:46:53 -08:00
Chris Fallin
704f5a5772 Cranelift/egraph mid-end: support merging effectful-but-idempotent ops (#5594)
* Support mergeable-but-side-effectful (idempotent) operations in general in the egraph's GVN.

This mirrors the similar change made in #5534.

* Add tests for egraph case.
2023-01-19 11:51:19 -08:00
Ulrich Weigand
a2e9a608c1 fuzzgen: Enable s390x and disable unimplemented ops (#5596)
Also fix assertion failure when using "i128 uext" or "i128 sext"
arguments or return values, as discovered by the fuzzer.
2023-01-19 10:08:32 -08:00
Kevin Rizzo
da03ff47f1 winch: Adding support for integration tests (#5588)
* Adding in the foundations for Winch `filetests`

This commit adds two new crates into the Winch workspace:
`filetests` and `test-macros`. The intent is to mimic the
structure of Cranelift `filetests`, but in a simpler way.

* Updates to documentation

This commits adds a high level document to outline how to test Winch
through the `winch-tools` utility. It also updates some inline
documentation which gets propagated to the CLI.

* Updating test-macro to use a glob instead of only a flat directory
2023-01-19 07:34:48 -05:00
Trevor Elliott
7cea73a81d Refactor BranchInfo::Table to no longer have an optional default branch (#5593) 2023-01-18 17:17:03 -08:00
Saúl Cabrera
94b51cdb17 winch: Use cranelift-codegen x64 backend for emission. (#5581)
This change substitutes the string based emission mechanism with
cranelift-codegen's x64 backend.

This change _does not_:

* Introduce new functionality in terms of supported instructions.
* Change the semantics of the assembler/macroassembler in terms of the logic to
emit instructions.

The most notable differences between this change and the previous version are:

* Handling of shared flags and ISA-specific flags, which for now are left with
the default value.
* Simplification of instruction emission per operand size: previously the
assembler defined different methods depending on the operand size (e.g. `mov`
for 64 bits, and `movl` for 32 bits). This change updates such approach so that
each assembler method takes an operand size as a parameter, reducing duplication
and making the code more concise and easier to integrate with the x64's `Inst` enum.
* Introduction of a disassembler for testing purposes.

As of this change, Winch generates the following code for the following test
programs:

```wat
(module
  (export "main" (func $main))

  (func $main (result i32)
        (i32.const 10)
        (i32.const 20)
        i32.add
        ))
```

```asm
   0:	55                   	push	rbp
   1:	48 89 e5             	mov	rbp, rsp
   4:	b8 0a 00 00 00       	mov	eax, 0xa
   9:	83 c0 14             	add	eax, 0x14
   c:	5d                   	pop	rbp
   d:	c3                   	ret
```

```wat
(module
  (export "main" (func $main))

  (func $main (result i32)
        (local $foo i32)
    (local $bar i32)
        (i32.const 10)
    (local.set $foo)
        (i32.const 20)
    (local.set $bar)

        (local.get $foo)
        (local.get $bar)
        i32.add
        ))
```

```asm
   0:	55                   	push	rbp
   1:	48 89 e5             	mov	rbp, rsp
   4:	48 83 ec 08          	sub	rsp, 8
   8:	48 c7 04 24 00 00 00 00	mov	qword ptr [rsp], 0
  10:	b8 0a 00 00 00       	mov	eax, 0xa
  15:	89 44 24 04          	mov	dword ptr [rsp + 4], eax
  19:	b8 14 00 00 00       	mov	eax, 0x14
  1e:	89 04 24             	mov	dword ptr [rsp], eax
  21:	8b 04 24             	mov	eax, dword ptr [rsp]
  24:	8b 4c 24 04          	mov	ecx, dword ptr [rsp + 4]
  28:	01 c1                	add	ecx, eax
  2a:	48 89 c8             	mov	rax, rcx
  2d:	48 83 c4 08          	add	rsp, 8
  31:	5d                   	pop	rbp
  32:	c3                   	ret
```

```wat
(module
  (export "main" (func $main))

  (func $main (param i32) (param i32) (result i32)
        (local.get 0)
        (local.get 1)
        i32.add
        ))
```

```asm
   0:	55                   	push	rbp
   1:	48 89 e5             	mov	rbp, rsp
   4:	48 83 ec 08          	sub	rsp, 8
   8:	89 7c 24 04          	mov	dword ptr [rsp + 4], edi
   c:	89 34 24             	mov	dword ptr [rsp], esi
   f:	8b 04 24             	mov	eax, dword ptr [rsp]
  12:	8b 4c 24 04          	mov	ecx, dword ptr [rsp + 4]
  16:	01 c1                	add	ecx, eax
  18:	48 89 c8             	mov	rax, rcx
  1b:	48 83 c4 08          	add	rsp, 8
  1f:	5d                   	pop	rbp
  20:	c3                   	ret
```
2023-01-18 06:58:13 -05:00
Trevor Elliott
1e6c13d83e cranelift: Rework block instructions to use BlockCall (#5464)
Add a new type BlockCall that represents the pair of a block name with arguments to be passed to it. (The mnemonic here is that it looks a bit like a function call.) Rework the implementation of jump, brz, and brnz to use BlockCall instead of storing the block arguments as varargs in the instruction's ValueList.

To ensure that we're processing block arguments from BlockCall values in instructions, three new functions have been introduced on DataFlowGraph that both sets of arguments:

inst_values - returns an iterator that traverses values in the instruction and block arguments
map_inst_values - applies a function to each value in the instruction and block arguments
overwrite_inst_values - overwrite all values in an instruction and block arguments with values from the iterator

Co-authored-by: Jamey Sharp <jamey@minilop.net>
2023-01-17 16:31:15 -08:00
Jamey Sharp
3a2ca67570 Generalize iterator types in compute_use_states (#5586)
This is a cleanup to help prepare for #5464.

Most of the diff is inlining the closure for `mark_all_uses_as_multiple`
which was only called once. That avoids some borrow-checker challenges.

The key change is that the former `push_args_on_stack` closure no longer
actually pushes the iterator on the stack, but just returns it. That
way this closure doesn't need the name of the stack's type. It also
allows it to be reused in the debug_assert.
2023-01-17 22:17:17 +00:00
Afonso Bordado
3ae373b073 cranelift: Disable select rule for i128 types on riscv64 (#5584)
* fuzzgen: Disable some selects for RISC-V

* cranelift: Force disable gen_select_reg rule for i128 values
2023-01-17 10:01:23 -08:00
Ayomide Bamidele
e4dc9c7944 Update Intel x86 CPU presets to match LLVM (#5490)
* Update Intel x86 CPU presets

* Add LLVM reference

* Remove 32bit CPU architectures

* Rename silvermont to slm

* Fix haswell presets

* Add icelake alias

* Group streaming simd presets

* Add slm silvermont preset

* Remove duplicate alderlake def
2023-01-13 21:02:36 +00:00
Saúl Cabrera
f0979af157 cranelift-codegen: Prepare aarch64 for usage from Winch (#5570)
This commit exposes the necessary aarch64 pieces to be used by Winch for binary emission.
2023-01-13 19:46:25 +00:00
Afonso Bordado
d3e6b7bd2a fuzzgen: Enable riscv64 and disable unimplemented ops (#5502) 2023-01-12 08:46:37 -08:00
Afonso Bordado
82494661c1 cranelift: Add atomic_{load,store} and fence to the interpreter (#5503)
* cranelift: Add `fence` to interpreter

* cranelift: Add `atomic_{load,store}` to the interpreter

* fuzzgen: Add `atomic_{load,store}`

* Update cranelift/fuzzgen/src/function_generator.rs

Co-authored-by: Jamey Sharp <jamey@minilop.net>

* fuzzgen: Use type size as the alignment size.

Co-authored-by: Jamey Sharp <jamey@minilop.net>
2023-01-12 08:36:04 -08:00
Saúl Cabrera
6cb68f3287 cranelift-codegen: Expose x64 settings (#5561)
Exposes x64 settings so that they can be consumed from Winch for binary emission.
2023-01-11 18:33:03 -05:00
Afonso Bordado
9556cb190f cranelift: Forbid argument extensions for floats and SIMD vectors (#5536)
* fuzzgen: Generate argument extensions only for integer argumetns

* cranelift: Add verifier check for argument extensions
2023-01-10 10:26:30 -08:00
Afonso Bordado
23ea435a91 fuzzgen: Reenable srem.i8 on x86 (#5545) 2023-01-09 12:30:57 -08:00
Afonso Bordado
8ac04612ae cranelift: Remove predicate not macro branch (#5552) 2023-01-09 12:19:30 -08:00
Afonso Bordado
f845ebb450 cranelift: Remove is_pic predicate from x86 backend (#5548)
This is still present as shared flags and we don't use the predicate anywhere.
2023-01-09 10:04:45 -08:00
Afonso Bordado
437f448a8d cranelift: Cleanup testing docs (#5549)
Removes some docs from tests that we no longer have.
Updates the ebb examples to the new block based examples.
2023-01-09 10:02:59 -08:00
Alexa VanHattum
44913825b5 cranelift: fix register for srem.i8 on x86_64 (#5540)
* Change register written to in specific srem case. Add regression test as filetest case. Fixes #5470

* Add another test case, newline

* Update comment
2023-01-06 22:18:16 +00:00
Jamey Sharp
e65a2c9280 cranelift-isle: Record all binding names (#5538)
...not just the ones at the outer scope of a rule.

Thanks to @avanhatt for pointing out that #5221 didn't capture as much
information as I intended it to.
2023-01-06 22:00:50 +00:00