Some REX-less encodings require an ABCD input because they are looking
at 8-bit registers. This constraint doesn't apply with a REX prefix
where the low 8 bits of all registers are addressable.
It can happen that the currently live registers are blocking a smaller
register class completely, so the only way of solving the allocation
problem is to turn some of the live-through registers into solver
variables.
When the quick_solve attempt fails, try to free up registers in the
critical register class by turning live-through values into solver
variables.
The brz and brnz instructions get support for 32-bit jump displacements
for long range branches.
Also change the way branch ranges are specified on tail recipes for the
Intel instructions. All branch displacements are relative to the end of
the instruction, so just compute the branch range origin as the
instruction size instead of trying to specify it in the tail recipe
definitions.
The x86_divmodx traps on integer overflow, but the srem instruction is
not supposed to trap with a -1 divisor.
Generate a legalization expansion for srem that special-cases the -1
divisor to simply return 0.
Also make sure we generate type checks for the controlling type variable
in legalization patterns. This is not needed for encodings since the
encoding tables are already keyed on the controlling type variable.
The native x86_fmin and x86_fmax instructions don't behave correctly for
NaN inputs and when comparing +0.0 to -0.0, so we need separate branches
for those cases.
These Intel-specific instructions represent the semantics of the minss /
maxss Intel instructions which behave more like a C ternary operator
than the WebAssembly fmin and fmax instructions.
They will be used as building blocks for implementing the WebAssembly
semantics.
This is used to represent the non-trapping semantics of the cvttss2si and
cvttsd2si instructions (and their vectorized counterparts).
The overflow behavior of this instruction is specific to the Intel ISAs.
There is no float-to-i64 instruction on the 32-bit Intel ISA.
Not all floating point condition codes are directly supported by the
ucimiss/ucomisd instructions. Some inequalities need to be reversed and
eq+ne require two separate tests.
These sign bit manipulations need to use a -0.0 floating point constant
which we didn't have a way of materializing previously.
Add a ieee32.bits(0x...) syntax to the Python AST nodes that creates am
f32 immediate value with the exact requested bitwise representation.
To begin with, these are catch-all encodings with a SIB byte and a
32-bit displacement, so they can access any stack slot via both the
stack pointer and the frame pointer.
In the future, we will add encodings for 8-bit displacements as well as
EBP-relative references without a SIB byte.
This contains encoding details for a stack reference: The base register
and offset to use in the specific instruction encoding.
Generate StackRef objects called in_stk0 etc for the binemit recipe
code. All binemit recipes need to compute base pointer offsets for stack
references, so have the automatically generated code do it.
A cursor now also remembers a current source location which will be
assigned to all new instructions created with the cursor.
The old layout::Cursor can't support source locations because it doesn't
have a reference to the full ir::Function.
These formats are not used any longer after the heap_load and heap_store
instructions were replaced by heap_addr.
Also drop the Uoffset32 immediate operand type which isn't used either.
Use the simplest expansion which materializes the bits of the floating
point constant as an integer and then bit-casts to the floating point
type. In the future, we may want to use constant pools instead. Either
way, we need custom legalization.
Also add a legalize_monomorphic() function to the Python targetISA class
which permits the configuration of a default legalization action for
monomorphic instructions, just like legalize_type() does for polymorphic
instructions.
This makes the details of the spiderwasm prologue configurable so it is
easier to modify SpiderMonkey without having to change Cretonne.
Create a stack object representing the SpiderMonkey prologue words
before calculating the stack layout so they won't be overwritten by
Cretonne's stack objects.
The flag guarantees that the generated function does not have any
internal return instructions. If the function returns at all, the return
must be the last instruction.
For now just implement a verifier check for this property. When we get
CFG simplifiers and block layout optimizations, they will need to heed
the flag.
Use these encodings to test trapz.b1 and trapnz.b1.
When a b1 value is stored in a register, only the low 8 bits are valid.
This is so we can use the various setCC instructions to generate the b1
registers.
The expansion of a heap_addr instruction depends on the type of heap and
its configuration, so this is handled by custom code.
Add a couple examples of heap access code to the language reference
manual.
Add preamble syntax for declaring static and dynamic heaps, and update
the langref section on heaps. Add IR support for heap references.
Remove the heap_load and heap_store as discussed in #144. We will use
heap_addr along with native load and store instructions in their place.
Add the heap_addr instruction and document its bounds checking
semantics.
The code to compute the address of a global variable depends on the kind
of variable, so custom legalization is required.
- Add a legalizer::globalvar module which exposes an
expand_global_addr() function. This module is likely to grow as we add
more types of global variables.
- Add a ArgumentPurpose::VMContext enumerator. This is used to represent
special 'vmctx' arguments that are used as base pointers for vmctx
globals.
