T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add Intel regmove encodings for floating point types.

Browse Source
This commit is contained in:
Jakob Stoklund Olesen
2017-09-27 12:36:27 -07:00
parent 1fe7890700
commit 44eab3e158
3 changed files with 20 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
cranelift/filetests/isa/intel/binary32-float.cton
View File

@@ -42,6 +42,11 @@ ebb0:
; asm: movaps %xmm5, %xmm2
[-,%xmm2] v19 = copy v10 ; bin: 0f 28 d5
; asm: movaps %xmm2, %xmm5
regmove v19, %xmm2 -> %xmm5 ; bin: 0f 28 ea
; asm: movaps %xmm5, %xmm2
regmove v19, %xmm5 -> %xmm2 ; bin: 0f 28 d5
; Binary arithmetic.
; asm: addss %xmm2, %xmm5
@@ -240,6 +245,11 @@ ebb0:
; asm: movaps %xmm5, %xmm2
[-,%xmm2] v19 = copy v10 ; bin: 0f 28 d5
; asm: movaps %xmm2, %xmm5
regmove v19, %xmm2 -> %xmm5 ; bin: 0f 28 ea
; asm: movaps %xmm5, %xmm2
regmove v19, %xmm5 -> %xmm2 ; bin: 0f 28 d5
; Binary arithmetic.
; asm: addsd %xmm2, %xmm5

2
lib/cretonne/meta/isa/intel/encodings.py
View File

@@ -358,6 +358,8 @@ I64.enc(base.bitcast.i64.f64, *r.rfumr.rex(0x66, 0x0f, 0x7e, w=1))
# movaps
enc_flt(base.copy.f32, r.furm, 0x0f, 0x28)
enc_flt(base.copy.f64, r.furm, 0x0f, 0x28)
enc_flt(base.regmove.f32, r.frmov, 0x0f, 0x28)
enc_flt(base.regmove.f64, r.frmov, 0x0f, 0x28)
# cvtsi2ss
enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)

8
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -321,6 +321,14 @@ rmov = TailRecipe(
modrm_rr(dst, src, sink);
''')
# XX /r, for regmove instructions (FPR version, RM encoded).
frmov = TailRecipe(
'frmov', RegMove, size=1, ins=FPR, outs=(),
emit='''
PUT_OP(bits, rex2(src, dst), sink);
modrm_rr(src, dst, sink);
''')
# XX /n with one arg in %rcx, for shifts.
rc = TailRecipe(
'rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0,