Commit Graph

45 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
e15c332471 Encode iconst.i32 for RISC-V.
For large constants with the low 12 bits clear, we already have the
"lui" encoding. Add "addi %x0" encodings for signed 12-bit constants.
2017-06-22 12:13:37 -07:00
Aleksey Kuznetsov
3693735874 Implement an iterator over encodings (#96)
* Implement an iterator over encodings

* Implement TargetIsa::legal_encodings

* Exclude non-boolean settings of isa flags bytes

* Address flake8 long line error
2017-06-19 08:52:19 -07:00
Jakob Stoklund Olesen
4503306f0e Add RISC-V encodings for call_indirect. 2017-06-14 16:14:16 -07:00
Jakob Stoklund Olesen
3e1e2b6e5e Add RISC-V encodings for copy instructions. 2017-06-14 15:36:25 -07:00
Jakob Stoklund Olesen
5336bbd4cc Add RISC-V encodings for spill and fill.
Add a Stack() class for specifying operand constraints for values on the
stack.

Add encoding recipes for RISC-V spill and fill instructions. Don't
implement the encoding recipe functions yet since we don't have the
stack slot layout yet.
2017-06-13 13:39:52 -07:00
Jakob Stoklund Olesen
f8a3a01f96 Add a few register utilities. 2017-05-08 13:39:26 -07:00
Jakob Stoklund Olesen
ee5f035e31 Upgrade to Rust 1.17.
- Remove some uses of 'static in const and static globals that are no
  longer needed.
- Use the new struct initialization shorthand.
2017-04-27 12:46:44 -07:00
Jakob Stoklund Olesen
6197bfff72 Add a TargetIsa::allocatable_registers() method.
This gives the target ISA a chance to reserve registers like the stack
pointer or hard-wired 0 registers like %x0 on RISC-V.
2017-04-26 13:54:40 -07:00
Jakob Stoklund Olesen
a4acc26d5a Add an enable_e setting for the RV32E instruction set.
This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.
2017-04-26 13:50:52 -07:00
Jakob Stoklund Olesen
e67f5e210f Add a TargetIsa::regclass_for_abi_type() function.
The legalize_signature() function will return ArgumentLoc::Reg arguments
that contain a register unit. However, the register also needs to be
able to associate a register class with the argument values to fully
track the used registers.

When values are defined by instructions, the register class is part for
the operand constraints for the instruction. For values defined on ABI
boundaries like function arguments and return values from a call, the
register class is provided by the new regclass_for_abi_type() function.

Provide implementations of this function in abi modules of all the
targets, even those that don't have a legalize_signature()
implementation yet.

Since we're adding abi modules to all targets, move the
legalize_signature() stubs in there and make the function mandatory in
TargetIsa. All targets will eventually need this function.
2017-04-26 10:29:18 -07:00
Jakob Stoklund Olesen
d66a9d196e Implement binary emission of RISC-V return instructions.
The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.
2017-04-19 16:26:04 -07:00
Jakob Stoklund Olesen
e44a5a4391 Append link and sret arguments in legalize_signature.
These special-purpose arguments and return values are only relevant for
the function being compiled, so add a `current` flag to
legalize_signature().

- Add the necessary argument values to the entry block to represent
  the special-purpose arguments.
- Propagate the link and sret arguments to return instructions if the
  legalized signature asks for it.
2017-04-19 15:55:12 -07:00
Jakob Stoklund Olesen
18b567f88e Flatten the Value reference representation.
All values are now references into the value table, so drop the
distinction between direct and table values. Direct values don't exist
any more.

Also remove the parser support for the 'vxNN' syntax. Only 'vNN' values
can be parsed now.
2017-04-12 14:45:22 -07:00
Jakob Stoklund Olesen
b165d9a313 Remove the first_type() methods from InstructionData.
Also remove the type field from all the variants. The type of the first
result value can be recovered from the value table now.
2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
28ff7b7925 Move the ctrl_typevar function into dfg.
Soon, InstructionData won't have sufficient information to compute this.

Give TargetIsa::encode() an explicit ctrl_typevar argument. This
function does not require the instruction to be inserted in the DFG
tables.
2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
4ee519e620 Add RISC-V call instruction encodings.
Calls are jal with a fixed %x1 link register.
2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V.
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
856a67ca3a Use EBB offsets for encoding RISC-V branches.
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
598c81c12e Add encoding size information to EncInfo.
Two new pieces of information are available for all encoding recipes:

- The size in bytes of an encoded instruction, and
- The range of a branch encoded with the recipe, if any.

In the meta language, EncRecipe takes two new constructor arguments. The
size is required for all encodings and branch_range is required for all
recipes used to encode branches.
2017-04-05 11:46:19 -07:00
Jakob Stoklund Olesen
f47c62ba8c Move encoding-related information into an EncInfo struct.
The tables returned by recipe_names() and recipe_constraints() are now
collected into an EncInfo struct that is available from
TargetIsa::encoding_info(). This is equivalent to the register bank
tables available fro TargetIsa::register_info().

This cleans of the TargetIsa interface and makes it easier to add
encoding-related information.
2017-04-05 10:07:19 -07:00
Jakob Stoklund Olesen
1984c96f7c rustfmt 0.8.1 2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz.
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V.
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui.
This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V.
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
9ddbc5d861 Emit Rshamt-type instructions for RISC-V.
These are the shift-by-immediate instructions.
2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
c9a14448b8 Emit I-type instructions for RISC-V.
These are the BinaryImm formats.
2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants.
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
0619d6f827 Generate binemit::emit_inst() functions.
Use the meta language encoding recipes to generate an emit_inst()
function for each ISA. The generated calls into recipe_*() functions
that must be implemented by hand.

Implement recipe_*() functions for the RISC-V recipes.

Add the TargetIsa::emit_inst() entry point which emits an instruction to
a CodeSink trait object.
2017-03-28 14:44:36 -07:00
Jakob Stoklund Olesen
010861d58e Upgrade to rustfmt 0.8.0.
Lots of changes this time.

Worked around what looks like a rustfmt bug in parse_inst_operands where
a large match was nested inside Ok().
2017-03-14 10:48:05 -07:00
Jakob Stoklund Olesen
2de210ddb6 Implement From traits on ArgAction for convenience. 2017-03-07 15:13:55 -08:00
Jakob Stoklund Olesen
40fc5da3d8 Heed uext and sext annotations on RISC-V arguments.
Translate the small integer arguments to i32 or i64 with the appropriate
extend and ireduce instructions.
2017-03-07 15:07:00 -08:00
Jakob Stoklund Olesen
37b2e94c72 Legalize entry block arguments to match ABI types.
Insert conversion code that reconstructs the original function argument
types from the legalized ABI signature.

Add abi::legalize_abi_value(). This function is used when adapting code
to a legalized function signature.
2017-03-07 13:29:19 -08:00
Jakob Stoklund Olesen
42e7021865 Implement legalize_signature for RISC-V.
Add an abi module with code that is probably useful to all ISAs when
implementing this function.

Add a unit() method to RegClassData which can be used to index the
register units in a class.
2017-03-03 11:09:55 -08:00
Jakob Stoklund Olesen
07f459fb93 Add a legalize_signature method to TargetIsa.
This entry point will be used for controlling ABI conventions when
legalizing.

Provide an empty implementation for RISC-V and let the other ISAs crash
in legalization.

This is just the scaffolding. We still need to:

- Rewrite the entry block arguments to match the legalized signature.
- Rewrite call and return instructions.
- Implement the legalize_signature() function for all ISAs.
- Add shared generic types to help with the legalize_signature()
  functions.
2017-03-03 11:00:26 -08:00
Jakob Stoklund Olesen
608d452f0c Compute the controlling type variable accurately.
Some polymorphic instructions don't return the controlling type
variable, so it has to be computed from the designated operand instead.

- Add a requires_typevar_operand() method to the operand constraints
  which indicates that.
- Add a ctrl_typevar(dfg) method to InstructionData which computes the
  controlling type variable correctly, and returns VOID for monomorphic
  instructions.
- Use ctrl_typevar(dfg) to drive the level-1 encoding table lookups.
2017-02-21 16:26:19 -08:00
Jakob Stoklund Olesen
1fa3ddf018 Return RegInfo by value from TargetIsa::register_info().
The struct is just a pair of static references, and we don't need the
double indirection.
2017-02-14 16:05:54 -08:00
Jakob Stoklund Olesen
933dfc70c1 Fix a dead code warning from the new Rust compiler.
On ISAs with no instruction predicates, just emit an unimplemented!()
stub for the check_instp() function. It is unlikely that a finished ISA
will not have any instruction predicates.
2017-02-03 11:28:59 -08:00
Jakob Stoklund Olesen
2390e3e3f0 Add operand register constraints.
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions.
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
e59b47c41a Return a Result from the TargetIsa::encode() method.
When an instruction can't be encoded, provide a viable legalization
action in the form of a Legalize enum.
2016-11-03 19:15:36 -07:00
Jakob Stoklund Olesen
80823b5fc4 Require documentation on cretonne public items. 2016-10-26 19:10:06 -07:00
Jakob Stoklund Olesen
31e033af49 File stale path references.
After rearranging the directory layout, some paths in documentation
needed updating.

Fix some typos too.
2016-10-24 13:27:10 -07:00
Jakob Stoklund Olesen
846db00a21 Move library crates under 'lib/'.
Give these crates each a more standard directory layout with sources in
a 'src' sub-sirectory and Cargo.toml in the top lib/foo directory.

Add license and description fields to each.

The build script for the cretonne crate now lives in
'lib/cretonne/build.rs' separating it from the normal library sources
under 'lib/cretonne/src'.
2016-10-17 14:44:43 -07:00