Commit Graph

705 Commits

Author SHA1 Message Date
Andrew Brown
0604ec480c Fix scalar_to_vector: move not wide enough for 64-bit values (#1287)
Previously, the use of `enc_x86_64` emitted two 64-bit mode encodings for `scalar_to_vector.i64`, neither of which contained the REX.W bit telling `MOVD/MOVQ` to move 64 bits of data instead of 32 bits. Now, `scalar_to_vector.i64` will always use a sole 64-bit mode REX.W encoding and `scalar_to_vector` with other widths will have three encodings: a 32-bit mode move, a 64-bit mode move with no REX, and a 64-bit mode move with REX (but not REX.W).
2019-12-16 10:17:08 -08:00
bjorn3
4cc0241f37 More i8 legalizations (#1253)
* Legalize stack_{load,store}.i8, fixes #433
* Legalize select.i8, cc: #466
* Legalize brz.i8 and brnz.i8, cc: #1117
2019-12-04 09:16:22 -08:00
krk
bc9f05e5e2 Add legalization for bitrev.i128 via narrowing, fixes #1116 (#1229) 2019-11-22 12:38:04 +01:00
Dan Gohman
b4528beaf5 Bump version to 0.51.0 (#1250) 2019-11-20 22:40:55 -08:00
bjorn3
c5e74986e1 Legalize uextend and sextend to 128bit ints 2019-11-19 14:42:21 -08:00
Andrew Brown
91d29c09d0 Add x86 SIMD floating-point absolute value 2019-11-15 13:45:25 -08:00
Andrew Brown
1f17e35e95 Add x86 SIMD immediate shifts 2019-11-15 13:45:25 -08:00
Andrew Brown
6519a43b08 Add x86 SIMD floating-point negation 2019-11-15 13:45:25 -08:00
krk
f7c7245b06 Add legalization for popcnt.i128 via narrowing, fixes #1116 2019-11-15 14:03:49 +01:00
Peter Huene
b578fd5396 Fix the cranelift-filetests build. (#1227)
This commit removes the dependency on `byteorder::ReadBytesExt`, which can't be
used from `no_std`, which is how we're building the `byteorder` crate.

The fix is to simply offset into the slice as needed rather than using a
`std::io::Cursor`.

Fixes #1225.
2019-11-13 16:22:26 -08:00
Andrew Brown
c8eb4e9612 Add x86 SIMD floating-point arithmetic 2019-11-12 17:05:39 -08:00
Andrew Brown
04db2a9f39 Bind constant vectors to vconst; fixes #1052 (#1217) 2019-11-12 15:57:59 -08:00
Benjamin Bouvier
9080a02e10 Replace CraneStation by bytecodealliance everywhere; (#1221) 2019-11-12 10:09:31 -08:00
Andrew Brown
d32301854d Add x86 SIMD implementation of float comparison 2019-11-08 14:06:53 -08:00
Benjamin Bouvier
143cb01489 Do not align the stack frame for leaf functions not using the stack. 2019-11-08 17:20:20 +01:00
Dan Gohman
cf82863ea9 Bump version to 0.49.0 (#1208) 2019-11-06 14:38:46 -08:00
Andrew Brown
af4637aff6 Add x86 SIMD legalizations for icmp less-than 2019-11-05 16:42:34 -08:00
Andrew Brown
feffed85d2 Add x86 SIMD legalizations for integer greater-than
This includes `icmp ugt`, `icmp sge`, and `icmp uge` for vectors with lanes of I8, I16, and I32.
2019-11-05 16:42:34 -08:00
Andrew Brown
0ab5760fd7 Add x86 SIMD instructions for min and max
Only the I8, I16, and I32 versions are included since Cranelift lacks support for AVX.
2019-11-05 16:42:34 -08:00
Andrew Brown
c454c3c771 Add x86 SIMD encoding for icmp sgt 2019-11-05 16:42:34 -08:00
Andrew Brown
e3a20d67b2 Add x86 SIMD legalization of icmp ne 2019-11-05 16:42:34 -08:00
Nick Fitzgerald
a49483408c Many multi-value returns (#1147)
* Add x86 encodings for `bint` converting to `i8` and `i16`

* Introduce tests for many multi-value returns

* Support arbitrary numbers of return values

This commit implements support for returning an arbitrary number of return
values from a function. During legalization we transform multi-value signatures
to take a struct return ("sret") return pointer, instead of returning its values
in registers. Callers allocate the sret space in their stack frame and pass a
pointer to it into the caller, and once the caller returns to them, they load
the return values back out of the sret stack slot. The callee's return
operations are legalized to store the return values through the given sret
pointer.

* Keep track of old, pre-legalized signatures

When legalizing a call or return for its new legalized signature, we may need to
look at the old signature in order to figure out how to legalize the call or
return.

* Add test for multi-value returns and `call_indirect`

* Encode bool -> int x86 instructions in a loop

* Rename `Signature::uses_sret` to `Signature::uses_struct_return_param`

* Rename `p` to `param`

* Add a clarifiying comment in `num_registers_required`

* Rename `num_registers_required` to `num_return_registers_required`

* Re-add newline

* Handle already-assigned parameters in `num_return_registers_required`

* Document what some debug assertions are checking for

* Make "illegalizing" closure's control flow simpler

* Add unit tests and comments for our rounding-up-to-the-next-multiple-of-a-power-of-2 function

* Use `append_isnt_arg` instead of doing the same thing  manually

* Fix grammar in comment

* Add `Signature::uses_special_{param,return}` helper functions

* Inline the definition of `legalize_type_for_sret_load` for readability

* Move sret legalization debug assertions out into their own function

* Add `round_up_to_multiple_of_type_align` helper for readability

* Add a debug assertion that we aren't removing the wrong return value

* Rename `RetPtr` stack slots to `StructReturnSlot`

* Make `legalize_type_for_sret_store` more symmetrical to `legalized_type_for_sret`

* rustfmt

* Remove unnecessary loop labels

* Do not pre-assign offsets to struct return stack slots

Instead, let the existing frame layout algorithm decide where they should go.

* Expand "sret" into explicit "struct return" in doc comment

* typo: "than" -> "then" in comment

* Fold test's debug message into the assertion itself
2019-11-05 14:36:03 -08:00
Dan Gohman
45fb377457 Bump version to 0.48.0 (#1202)
* Bump version to 0.48.0

* Re-enable `byteorder`'s default features.

The code uses `WriteBytesExt` which depends on the `std` feature being
enabled. So for now, just enable `std`.
2019-11-05 13:59:19 -08:00
Peter Huene
8923bac7e8 Implement emitting Windows unwind information for fastcall functions. (#1155)
* Implement emitting Windows unwind information for fastcall functions.

This commit implements emitting Windows unwind information for x64 fastcall
calling convention functions.

The unwind information can be used to construct a Windows function table at
runtime for JIT'd code, enabling stack walking and unwinding by the operating
system.

* Address code review feedback.

This commit addresses code review feedback:

* Remove unnecessary unsafe code.
* Emit the unwind information always as little endian.
* Fix comments.

A dependency from cranelift-codegen to the byteorder crate was added.
The byteorder crate is a no-dependencies crate with a reasonable
abstraction for writing binary data for a specific endianness.

* Address code review feedback.

* Disable default features for the `byteorder` crate.
* Add a comment regarding the Windows ABI unwind code numerical values.
* Panic if we encounter a Windows function with a prologue greater than 256
  bytes in size.
2019-11-05 13:14:30 -08:00
Dan Gohman
a9868de3d8 Bump version to 0.47.0 2019-11-04 15:43:27 -08:00
Peter Huene
9f506692c2 Fix clippy warnings.
This commit fixes the current set of (stable) clippy warnings in the repo.
2019-10-24 17:20:12 -07:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
2019-10-22 11:01:05 -07:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
8f74333662 Add x86 SIMD band_not 2019-10-17 15:49:29 -07:00
Sean Stangl
fad6bb1a5c Fix build by marking tests as incompatible with basic-blocks. Closes #1152 2019-10-17 12:00:22 -07:00
Benjamin Bouvier
a3f55cdf1f Regalloc solver: check that a variable doesn't exist to test if it can be added (fixes #1123);
This situation could be triggered that can_add_var would return true
while a variable was already added for the given register.

For instance, when we have a reassignment (because of a fixed register
input requirement) and a fixed input conflict on the same fixed
register, this register will not be available in the regs_in set after
inputs_done (because of the fixed input conflict diversion) but will
have its own variable.
2019-10-17 08:42:08 -07:00
Nicolas B. Pierron
7c31ce40c4 i128-isplit-forward-jump.clif: BB conditional branches can only be followed by a jump statement. 2019-10-17 13:59:04 +02:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
2019-10-15 15:51:50 -07:00
Dan Gohman
50b7d2827d Bump version to 0.46.1 2019-10-15 11:11:48 -07:00
Dan Gohman
ac4e93f971 Bump version to 0.46.0 2019-10-15 09:43:28 -07:00
Andrew Brown
1f728c1797 Add x86 legalization for SIMD bnot 2019-10-11 11:05:24 -07:00
Andrew Brown
dbe7dd59da Add x86 SIMD bxor 2019-10-11 11:05:24 -07:00
Andrew Brown
4cdc1e76a4 Add x86 SIMD band 2019-10-11 11:05:24 -07:00
Ujjwal Sharma
f1c25c2c5a [codegen] legalize imul for 64-bit and 128-bit operands
Add a legalization that legalizes imul.I64 for 32-bit ISAs and imul.I128
for 64-bit (and subsequently 32-bit) ISAs.

Refs: https://github.com/bnjbvr/cranelift-x86/issues/4
2019-10-10 17:39:40 +02:00
Ujjwal Sharma
c062f12d7c [codegen] legalize icmp for 64 and 128 bit operands
Add legalizations for icmp and icmp_imm for i64 and i128 operands for
the narrow legalization set, allowing 32-bit ISAs (like x86-32) to
compare 64-bit integers and all ISAs to compare 128-bit integers.

Fixes: https://github.com/bnjbvr/cranelift-x86/issues/2
2019-10-10 11:06:19 +02:00
bjorn3
68b671e0ee Fix isplit legalization for ebb params when jumping forward
Fixes #1106
2019-10-09 08:56:48 -07:00
Dan Gohman
ece9450a2f Bump version to 0.45.0 2019-10-09 06:20:30 -07:00
Benjamin Bouvier
cbbd94db02 Allow wrap-around when subtracting type size to immediate in try_fold_extended_move; 2019-10-08 20:16:48 +02:00
Benjamin Bouvier
a9d9f9f135 Write a run test for brz.i128; 2019-10-02 13:43:44 +02:00
Nicolas B. Pierron
e0005f1e6c Insert split-edge of conditional branches before the destination. 2019-10-02 12:03:56 +02:00
bjorn3
093b3b3426 Fix brz.i128
Fixes #1066
2019-10-02 11:04:29 +02:00
Andrew Brown
d8967bb58a Split SIMD arithmetic tests by test directive 2019-09-30 13:54:30 -07:00
Andrew Brown
90c49a2f7c Add saturating subtraction with a SIMD encoding
This includes the new instructions `ssub_sat` and `usub_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-subtraction).
2019-09-30 13:54:30 -07:00