Add x86 SIMD floating-point negation

cranelift/codegen/meta/src/isa/x86/legalize.rs

@@ -2,6 +2,7 @@ use crate::cdsl::ast::{constant, var, ExprBuilder, Literal};
 use crate::cdsl::instructions::{vector, Bindable, InstructionGroup};
 use crate::cdsl::types::{LaneType, ValueType};
 use crate::cdsl::xform::TransformGroupBuilder;
+use crate::shared::types::Float::{F32, F64};
 use crate::shared::types::Int::{I16, I32, I64, I8};
 use crate::shared::Definitions as SharedDefinitions;
 
@@ -37,6 +38,8 @@ pub(crate) fn define(shared: &mut SharedDefinitions, x86_instructions: &Instruct
     let fcvt_to_uint_sat = insts.by_name("fcvt_to_uint_sat");
     let fmax = insts.by_name("fmax");
     let fmin = insts.by_name("fmin");
+    let fneg = insts.by_name("fneg");
+    let fsub = insts.by_name("fsub");
     let iadd = insts.by_name("iadd");
     let icmp = insts.by_name("icmp");
     let iconst = insts.by_name("iconst");
@@ -543,6 +546,14 @@ pub(crate) fn define(shared: &mut SharedDefinitions, x86_instructions: &Instruct
         narrow.legalize(def!(c = icmp_(ule, a, b)), vec![def!(c = icmp(uge, b, a))]);
     }
 
+    for ty in &[F32, F64] {
+        let fneg = fneg.bind(vector(*ty, sse_vector_size));
+        narrow.legalize(
+            def!(b = fneg(a)),
+            vec![def!(c = vconst(u128_zeroes)), def!(b = fsub(c, a))],
+        );
+    }
+
     narrow.custom_legalize(shuffle, "convert_shuffle");
     narrow.custom_legalize(extractlane, "convert_extractlane");
     narrow.custom_legalize(insertlane, "convert_insertlane");

cranelift/filetests/filetests/isa/x86/simd-arithmetic-legalize.clif

@@ -34,3 +34,18 @@ ebb0:
 
     return
 }
+
+function %fneg_legalized() {
+ebb0:
+    v0 = vconst.f32x4 [0x1.0 0x2.0 0x3.0 0x4.0]
+    v1 = fneg v0
+    ; check: v4 = vconst.f32x4 0x00
+    ; nextln: v1 = fsub v4, v0
+
+    v2 = vconst.f64x2 [0x1.0 0x2.0]
+    v3 = fneg v2
+    ; check: v5 = vconst.f64x2 0x00
+    ; nextln: v3 = fsub v5, v2
+
+    return
+}

cranelift/filetests/filetests/isa/x86/simd-arithmetic-run.clif

@@ -214,7 +214,6 @@ ebb0:
 }
 ; run
 
-
 function %fmin_f64x2() -> b1 {
 ebb0:
     v0 = vconst.f64x2 [-0x1.0 -0x1.0]
@@ -227,3 +226,16 @@ ebb0:
     return v4
 }
 ; run
+
+function %fneg_f64x2() -> b1 {
+ebb0:
+    v0 = vconst.f64x2 [0x1.0 -0x1.0]
+    v1 = fneg v0
+
+    v2 = vconst.f64x2 [-0x1.0 0x1.0]
+    v3 = fcmp eq v1, v2
+    v4 = vall_true v3
+
+    return v4
+}
+; run