Commit Graph

724 Commits

Author SHA1 Message Date
Andrew Brown
d3df275003 Remove duplication of map_reg; fixes #1245
Both cranelift-codegen and wasmtime-debug need to map Cranelift registers to Gimli registers. Previously both crates had an almost-identical `map_reg` implementation. This change:
 - removes the wasmtime-debug implementation
 - improves the cranelift-codegen implementation with custom errors
 - exposes map_reg in `cranelift_codegen::isa::fde::map_reg` and subsequently `wasmtime_environ::isa::fde::map_reg`
2020-03-31 15:42:02 -07:00
Andrew Brown
54398156ea Add x86 implementation of SIMD load_extend instructions 2020-03-31 11:35:26 -07:00
Andrew Brown
cf1cfdcace Add new instructions to support SIMD load_extend 2020-03-31 11:35:26 -07:00
bjorn3
dfe22836e8 Fix the order of the rex2 registers for r_ib_unsigned_gpr (#1424)
Fixes #1423
2020-03-27 14:29:32 -07:00
Dan Gohman
6fa9be7767 Wasmtime 0.13.0 and Cranelift 0.61.0. (#1398)
This also updates the publishing scripts to work with newly added
and reorganized crates.
2020-03-26 13:19:02 -07:00
Benjamin Bouvier
1d5a678124 Fixes #1240: Add a new accessor to indicate that an opcode requires spilling all registers; 2020-03-23 12:19:28 +01:00
Alex Crichton
5bd03d282f Update a number of wasmtime's dependencies (#1355)
* Run `cargo update`
* Use `cargo outdated` to guide some manual version bumps
2020-03-18 14:15:33 -05:00
Andrew Brown
0d63bd12d8 Infer REX prefix for SIMD operations; fixes #1127
- Convert recipes to have necessary size calculator
- Add a missing binemit function, `put_dynrexmp3`
- Modify the meta-encodings of x86 SIMD instructions to use `infer_rex()`, mostly through the `enc_both_inferred()` helper
- Fix up tests that previously always emitted a REX prefix
2020-03-18 10:12:50 -07:00
Andrew Brown
e1d3930ce4 Add SIMD store_complex 2020-03-17 19:37:55 -07:00
Andrew Brown
368094a95b Add SIMD load_complex 2020-03-17 19:37:55 -07:00
Andrew Brown
bda9d7cfa6 Add SIMD copy_to_ssa 2020-03-17 19:37:55 -07:00
Andrew Brown
8598295bc4 Remove FPR32; fixes #1303
Until #1306 is resolved (some spilling/regalloc issue with larger FPR register banks), this removes FPR32 support. Only Wasm's `i64x2.mul` was using this register class and that instruction is predicated on AVX512 support; for the time being, that instruction will have to make do with the 16 FPR registers.
2020-03-17 12:46:41 -07:00
Nathan Froyd
af709ded94 bump cranelift version to 0.60.0 (#1328) 2020-03-17 15:29:20 -04:00
Andrew Brown
444d021ede Add x86 implementation of fcvt_from_sint 2020-03-17 10:52:03 -07:00
Yury Delendik
f76b36f737 Write .debug_frame information (#53)
* Write .debug_frame information

* mv map_reg
2020-03-11 10:22:51 -05:00
Till Schneidereit
8f824a9fc1 Update outdated references to the Cranelift repository
This patch updates or removes all references to the Cranelift repository. It affects links in README documents, issues that were transferred to the Wasmtime repository, CI badges, and a small bunch of sundry items.
2020-03-09 14:06:24 +01:00
Andrew Brown
fa7481a681 Add x86 implementation of SIMD swizzle instruction 2020-03-06 15:49:53 -08:00
Andrew Brown
442edf5c84 Refactor SIMD legalizations to separate define* function
See https://github.com/bytecodealliance/wasmtime/issues/1168
2020-03-06 14:57:11 -08:00
Andrew Brown
6e0401b83a Refactor SIMD lane instructions to separate define* function 2020-03-06 14:57:11 -08:00
Andrew Brown
7f7196a655 Add i64x2 integer multiplication using AVX512DQ 2020-03-06 10:53:22 -08:00
Andrew Brown
7d5075a649 Rename RexRecipeKind to RecipePrefixKind 2020-03-06 10:53:22 -08:00
Andrew Brown
2216f90916 Add an EVEX recipe (and associated recipe infrastructure) for encoding a binary operation 2020-03-06 10:53:22 -08:00
Andrew Brown
965714d675 Add encoding functions for emitting EVEX formats
Only the `reg, vvvv, rm` form is currently supported but it should not be difficult to add more forms.
2020-03-06 10:53:22 -08:00
Andrew Brown
079fcafcb1 Expand x86 registers to include 32 XMM registers
The EVEX encoding format (e.g. in AVX-512) allows addressing 32 registers instead of 16. The FPR register class currently defines 16 registers, `%xmm0`-`%xmm15`; that class is kept as-is with this change. A larger class, FPR32, is added as a super-class of FPR using a larger bank of registers, `%xmm0`-`%xmm31`.
2020-03-06 10:53:22 -08:00
Andrew Brown
1d15054310 Remove the debug crate's hard-coded dependency on register ordering 2020-03-06 10:53:22 -08:00
Andrew Brown
3f53bcb740 Remove dependency on hard-coded ordering of x86 register banks
With this change, register banks can now be re-ordered and other components (e.g. unwinding, regalloc) will no longer break. The previous behavior assumed that GPR registers always started at `RegUnit` 0.
2020-03-06 10:53:22 -08:00
Andrew Brown
518c7526d2 Fix incorrect register calculation in RegBank::unit_by_name 2020-03-06 10:53:22 -08:00
Andrew Brown
baf71f5a5f Add AVX-related settings
Many more settings are possible but this subset is required in order to distinguish instructions that can use EVEX encodings.
2020-03-06 10:53:22 -08:00
Alex Crichton
3179dcf6f1 Update Cranelift's documentation after the merger. (#1238)
Update the documentation for the merger, and also for various changes in
Cranelift. Remove some old obsolete documentation, and convert the remaining
Sphinx files to Markdown. Some of the remaining content is still out of
date, but this is a step forward.
2020-03-05 15:51:12 -06:00
Ryan Hunt
4aa8776a9b Skip non-branching blocks now that we're using basic blocks
This is a rebase of [1]. In the long term, we'll want to simplify these
analysis passes. For now, this is simple and will reduce the number of
instructions processed in certain cases.

[1] https://github.com/bytecodealliance/cranelift/pull/866
2020-03-05 16:11:13 +01:00
Ryan Hunt
07f335dca6 Rename 'an block' to 'a block'
Missed this in the automatic rename of 'Ebb' to 'Block'.
2020-03-03 13:21:13 -06:00
Alex Crichton
5f1cba0b7f Hook up all crates via path dependencies 2020-02-28 09:16:05 -08:00
bjorn3
0a1bb3ba6c Add TLS support for ELF and MachO (#1174)
* Add TLS support
* Add binemit and legalize tests
* Spill all caller-saved registers when necessary
2020-02-25 17:50:04 -08:00
Dan Gohman
0a11736fbf Bump version to 0.59.0 (#1406) 2020-02-24 15:10:08 -08:00
Andrew Brown
032e81fd6f Add x86 SIMD average rounding 2020-02-24 09:48:38 -08:00
Andrew Brown
3ae1af1ad2 Add new Cranelift instructions for integer min/max
This includes legalizations to the previously-existing x86 SIMD integer min/max.
2020-02-21 09:33:43 -08:00
Andrew Brown
7dfd159fd8 Avoid unused import warnings in generated legalizer code (#1393) 2020-02-20 09:58:19 -08:00
Andrew Brown
1a9dc743d1 Infer REX prefix for SIMD load instruction 2020-02-19 09:24:05 -08:00
Andrew Brown
936120dcf9 Infer REX prefix for SIMD store and vconst instructions 2020-02-19 09:24:05 -08:00
Peter Delevoryas
18b40d1101 Add ineg legalization for scalar integer types (#1385) 2020-02-14 13:16:02 -08:00
Y-Nak
58e5a62cde Fix inverted result of is_leaf method 2020-02-13 11:02:22 +01:00
Dan Gohman
376654bdfc Bump version to 0.58.0 (#1382) 2020-02-07 13:58:06 -08:00
Ryan Hunt
832666c45e Mass rename Ebb and relatives to Block (#1365)
* Manually rename BasicBlock to BlockPredecessor

BasicBlock is a pair of (Ebb, Inst) that is used to represent the
basic block subcomponent of an Ebb that is a predecessor to an Ebb.

Eventually we will be able to remove this struct, but for now it
makes sense to give it a non-conflicting name so that we can start
to transition Ebb to represent a basic block.

I have not updated any comments that refer to BasicBlock, as
eventually we will remove BlockPredecessor and replace with Block,
which is a basic block, so the comments will become correct.

* Manually rename SSABuilder block types to avoid conflict

SSABuilder has its own Block and BlockData types. These along with
associated identifier will cause conflicts in a later commit, so
they are renamed to be more verbose here.

* Automatically rename 'Ebb' to 'Block' in *.rs

* Automatically rename 'EBB' to 'block' in *.rs

* Automatically rename 'ebb' to 'block' in *.rs

* Automatically rename 'extended basic block' to 'basic block' in *.rs

* Automatically rename 'an basic block' to 'a basic block' in *.rs

* Manually update comment for `Block`

`Block`'s wikipedia article required an update.

* Automatically rename 'an `Block`' to 'a `Block`' in *.rs

* Automatically rename 'extended_basic_block' to 'basic_block' in *.rs

* Automatically rename 'ebb' to 'block' in *.clif

* Manually rename clif constant that contains 'ebb' as substring to avoid conflict

* Automatically rename filecheck uses of 'EBB' to 'BB'

'regex: EBB' -> 'regex: BB'
'$EBB' -> '$BB'

* Automatically rename 'EBB' 'Ebb' to 'block' in *.clif

* Automatically rename 'an block' to 'a block' in *.clif

* Fix broken testcase when function name length increases

Test function names are limited to 16 characters. This causes
the new longer name to be truncated and fail a filecheck test. An
outdated comment was also fixed.
2020-02-07 10:46:47 -06:00
Nick Fitzgerald
19a188789b Bump to 0.57.0 (#1375)
* Update wasmparser to 0.48.2

* Bump to version 0.57.0
2020-02-04 16:18:59 +01:00
Yury Delendik
169dbef784 Properly preserve and restore CFA state in FDE (#1373)
* Properly preserve and restore CFA state in FDE
2020-02-03 14:08:40 -08:00
Joshua Nelson
5edf015ada Make get_libcall_funcref pub(crate) (#1291)
* Make `get_libcall_funcref` `pub(crate)`

Closes https://github.com/bytecodealliance/cranelift/issues/1273.

Since get_libcall_funcref is only used internally by the verifier,
it doesn't make sense to have it be public. This will encourage users to
look elsewhere for `memcpy` (they should be looking at
https://docs.rs/cranelift-frontend/0.51.0/cranelift_frontend/struct.FunctionBuilder.html#method.emit_small_memcpy)
2020-01-24 16:43:44 +01:00
Ryan Hunt
c360007b19 Drop 'basic-blocks' feature (#1363)
* All: Drop 'basic-blocks' feature

This makes it so that 'basic-blocks' cannot be disabled and we can
start assuming it everywhere.

* Tests: Replace non-bb filetests with bb version

* Tests: Adapt solver-fixedconflict filetests to use basic blocks
2020-01-23 22:36:06 -07:00
Ryan Hunt
946251e655 Codegen: Align representation of stackmap with SpiderMonkey
This commit aligns the representation of stackmaps to be the same
as Spidermonkey's by:
 * Reversing the order of the bitmap from low addresses to high addresses
 * Including incoming stack arguments
 * Excluding outgoing stack arguments

Additionally, some accessor functions were added to allow Spidermonkey
to access the internals of the bitmap.
2020-01-23 13:37:11 -06:00
Ryan Hunt
bbc0a328c7 Codegen: Allow encoding of (r32|r64).(load|store)
Accessing Wasm reference globals that are reference types will
want to use the plain load/store instructions. This commit adds
encodings for these instructions to match loading a i32/i64.
Producers of IR are required to insert the appropriate barriers
around the loads/stores.
2020-01-23 13:37:11 -06:00
Ryan Hunt
848baa0aa7 Codegen: Add ref.is_invalid instruction
Spidermonkey returns a sentinel ref value of '-1' from some VM functions
to indicate failure. This commit adds an instruction analagous to ref.is_null
that checks for this value.
2020-01-23 13:37:11 -06:00