Commit Graph

8716 Commits

Author SHA1 Message Date
Afonso Bordado
f25f5b2732 aarch64: Implement lowering uextend/sextend for i128 values 2021-06-22 12:24:07 +01:00
Alex Crichton
8760bccc8e Fix running enter/exit hooks on start functions (#3001)
This commit fixes running the store's enter/exit hooks into wasm which
accidentally weren't run for an instance's `start` function. The fix
here was mostly to just sink the enter/exit hook much lower in the code
to `invoke_wasm_and_catch_traps`, which is the common entry point for
all wasm calls.

This did involve propagating the `StoreContext<T>` generic rather than
using `StoreOpaque` unfortunately, but it is overally not too too much
code and we generally wanted most of it inlined anyway.
2021-06-21 16:31:10 -05:00
Chris Fallin
18cd2f681c Merge pull request #3002 from afonso360/aarch64-i128-br
aarch64 implement brz,brnz,br_icmp for i128 values
2021-06-21 10:52:50 -07:00
Anton Kirilov
cb93726250 Enable more tests on AArch64 (#2994)
Copyright (c) 2021, Arm Limited.
2021-06-21 12:26:44 -05:00
Chris Fallin
443eb7a843 Merge pull request #3007 from bjorn3/hand_written_legalization
Use hand written legalizations in simple_legalize
2021-06-21 09:59:35 -07:00
Chris Fallin
444d9f9726 Merge pull request #3008 from afonso360/aarch64-i128-ireduce
aarch64: Implement ireduce for i128 values
2021-06-21 09:54:43 -07:00
Chris Fallin
4246e69c1c Merge pull request #3004 from afonso360/aarch64-i128-rotates
aarch64: Implement lowering rotl/rotr for i128 values
2021-06-21 09:53:57 -07:00
Chris Fallin
a24f0946e9 Merge pull request #2997 from akirilov-arm/simd_i8x16_arith2
Enable the simd_i8x16_arith2 test for AArch64
2021-06-21 09:20:43 -07:00
Chris Fallin
54a64ff810 Merge pull request #3010 from alexcrichton/fix-dylib
Connect helper C symbols to their static library
2021-06-21 08:54:33 -07:00
Alex Crichton
724beaf0f3 Connect helper C symbols to their static library
This commit adds a `#[link]` annotation to the block defining symbols
coming from a native static library that we build and link. This is
required by rustc to get symbols to get exported correctly when linking
wasmtime into a Rust dynamic library instead of always as an rlib.

While I was at it I went ahead and renamed the symbols now that they're
no longer in C++ and they're doing setjmp/longjmp and not much else.

Closes #3006
2021-06-21 07:27:22 -07:00
Afonso Bordado
151ad2f338 aarch64: Implement ireduce for i128 values 2021-06-20 19:04:45 +01:00
bjorn3
fa6e52848c Fix warnings 2021-06-20 18:52:48 +02:00
bjorn3
1415dd824a Remove all dsl legalizations for arm32, arm64 and s390x 2021-06-20 18:43:45 +02:00
bjorn3
50e53a0a73 Use hand written legalizations in simple_legalize
This allows removal of the legalization dsl once the old backends are
removed.
2021-06-20 18:43:38 +02:00
Afonso Bordado
f7f52445c8 aarch64: Implement lowering rotl/rotr for i128 values 2021-06-20 15:53:56 +01:00
Afonso Bordado
da4daa6f32 cranelift: Expand i128 extend testcases 2021-06-20 09:26:09 +01:00
Afonso Bordado
45faace329 aarch64: Implement i128 br_icmp
The previous commit deduplicated the icmp impl, so we reuse that
but make modifications where we don't need to set the results.
2021-06-19 22:01:33 +01:00
Afonso Bordado
b5708b4386 aarch64: Deduplicate lowering icmp
Lowering icmp was duplicated across callers that only cared about
flags, and callers that only cared about the bool result.

Merge both callers into `lower_icmp` which does the correct thing
depending on a new IcmpOutput parameter.
2021-06-19 08:32:37 +01:00
Alex Crichton
7ce46043dc Add guard pages to the front of linear memories (#2977)
* Add guard pages to the front of linear memories

This commit implements a safety feature for Wasmtime to place guard
pages before the allocation of all linear memories. Guard pages placed
after linear memories are typically present for performance (at least)
because it can help elide bounds checks. Guard pages before a linear
memory, however, are never strictly needed for performance or features.
The intention of a preceding guard page is to help insulate against bugs
in Cranelift or other code generators, such as CVE-2021-32629.

This commit adds a `Config::guard_before_linear_memory` configuration
option, defaulting to `true`, which indicates whether guard pages should
be present both before linear memories as well as afterwards. Guard
regions continue to be controlled by
`{static,dynamic}_memory_guard_size` methods.

The implementation here affects both on-demand allocated memories as
well as the pooling allocator for memories. For on-demand memories this
adjusts the size of the allocation as well as adjusts the calculations
for the base pointer of the wasm memory. For the pooling allocator this
will place a singular extra guard region at the very start of the
allocation for memories. Since linear memories in the pooling allocator
are contiguous every memory already had a preceding guard region in
memory, it was just the previous memory's guard region afterwards. Only
the first memory needed this extra guard.

I've attempted to write some tests to help test all this, but this is
all somewhat tricky to test because the settings are pretty far away
from the actual behavior. I think, though, that the tests added here
should help cover various use cases and help us have confidence in
tweaking the various `Config` settings beyond their defaults.

Note that this also contains a semantic change where
`InstanceLimits::memory_reservation_size` has been removed. Instead this
field is now inferred from the `static_memory_maximum_size` and guard
size settings. This should hopefully remove some duplication in these
settings, canonicalizing on the guard-size/static-size settings as the
way to control memory sizes and virtual reservations.

* Update config docs

* Fix a typo

* Fix benchmark

* Fix wasmtime-runtime tests

* Fix some more tests

* Try to fix uffd failing test

* Review items

* Tweak 32-bit defaults

Makes the pooling allocator a bit more reasonable by default on 32-bit
with these settings.
2021-06-18 09:57:08 -05:00
Anton Kirilov
b09b123a9e Enable the simd_i8x16_arith2 test for AArch64
Copyright (c) 2021, Arm Limited.
2021-06-18 14:09:52 +01:00
Afonso Bordado
a26be628bc aarch64: Implement lowering brz,brnz for i128 values 2021-06-18 00:21:54 +01:00
Alex Crichton
d8d4bf81b2 Reimplement how instance exports are stored/loaded (#2984)
* Reimplement how instance exports are stored/loaded

This commit internally refactors how instance exports are handled and
fixes two issues. One issue is that when we instantiate an instance we
no longer forcibly load all items from the instance immediately,
deferring insertion of each item into the store data tables to happen
later as necessary. The next issue is that repeated calls to
`Caller::get_export` would continuously insert items into the store data
tables. While working as intended this was undesirable because it would
continuously push onto a vector that only got deallocated once the
entire store was deallocate. Now it's routed to `Instance::get_export`
which doesn't have this behavior.

Closes #2916
Closes #2983

* Just define our own `Either`
2021-06-17 14:27:48 -05:00
Chris Fallin
5ddf562309 Merge pull request #2991 from uweigand/s390x-z14
s390x: Add z14 support
2021-06-17 08:24:23 -07:00
Chris Fallin
de1edd4976 Merge pull request #2985 from afonso360/aarch64-i128-load-store
aarch64: Implement I128 Loads and Stores
2021-06-17 08:23:15 -07:00
Afonso Bordado
c82764605f aarch64: Add i128 load & store tests and refactor address calculation
The previous address calculation code had a bug where we tried to
add offsets into a temporary register before defining it, causing
the regalloc to complain.
2021-06-17 15:50:08 +01:00
Ulrich Weigand
def54fb1fa s390x: Add z14 support
* Add support for processor features (including auto-detection).

* Move base architecture set requirement back to z14.

* Add z15 feature sets and re-enable z15-specific code generation
  when required features are available.
2021-06-17 10:23:15 +02:00
Alex Crichton
fb07ff5740 Implement Clone for Linker (#2993)
There's no real reason to not do this, and it can help with some
usability use cases!
2021-06-16 16:06:24 -05:00
Chris Fallin
8ac83a2c63 Merge pull request #2990 from afonso360/aarch64-bitops-count
aarch64: Add i128 bit counting instructions
2021-06-16 10:25:45 -07:00
Afonso Bordado
9fc89d2316 aarch64: Add bitrev,clz,cls,ctz for i128 values 2021-06-16 10:44:10 +01:00
Afonso Bordado
09fec151eb aarch64: Add popcnt for i128 values 2021-06-16 10:44:10 +01:00
Alex Crichton
5140fd251a Update wasm-tools crates (#2989)
* Update wasm-tools crates

This brings in recent updates, notably including more improvements to
wasm-smith which will hopefully help exercise non-trapping wasm more.

* Fix some wat
2021-06-15 22:56:10 -05:00
Chris Fallin
53006ef0de Merge pull request #2988 from uweigand/s390x-atomic-part1
s390x: Add support for atomic operations (part 1)
2021-06-15 10:50:35 -07:00
Ulrich Weigand
46b73431ca s390x: Add support for atomic operations (part 1)
This adds full back-end support for the Fence, AtomicLoad
and AtomicStore operations, and partial support for the
AtomicCas and AtomicRmw operations.

The missing pieces include sub-word operations, operations
on little-endian memory requiring byte-swapping, and some
of the subtypes of AtomicRmw -- everything that cannot be
implemented without a compare-and-swap loop.  This will be
done in a follow-up patch.

This patch already suffices to make the test suite green
again after a recent change that now requires atomic
operations when accessing the heap.
2021-06-15 17:12:11 +02:00
Olivier Lemasle
a7dad4e38f Include READMEs in crates (#2987) 2021-06-15 06:40:45 -07:00
Afonso Bordado
1c05e06bd5 aarch64: Implement I128 Loads and Stores 2021-06-14 21:56:53 +01:00
Pat Hickey
57375588f2 Merge pull request #2976 from bjorn3/aarch64-object
Lower Arm64Call relocations in cranelift-object
2021-06-13 13:59:06 -07:00
bjorn3
e9f3ac2068 Update object 2021-06-12 12:02:09 +02:00
Olivier Lemasle
b506bc30b1 wasmtime-cache: Update zstd (#2969)
Also update exceptions in deny.toml bans
2021-06-10 12:47:45 -05:00
bjorn3
7d23a9daf7 Lower Arm64Call relocations in cranelift-object 2021-06-10 12:54:25 +02:00
Chris Fallin
3d56728b86 Merge pull request #2975 from afonso360/aarch64-icmp
aarch64: Implement lowering i128 icmp instructions
2021-06-09 15:38:41 -07:00
Chris Fallin
caa85c2fa5 Merge pull request #2959 from afonso360/aarch64-i128-bit-ops
aarch64 add basic i128 bit ops
2021-06-09 15:21:54 -07:00
Afonso Bordado
2643d2654c aarch64: Implement lowering i128 icmp instructions
We have 3 different aproaches depending on the type of comparision requested:
* For eq/ne we compare the high bits and low bits and check
  if they are equal
* For overflow checks, we perform a i128 add and check the
  resulting overflow flag
* For the remaining comparisions (gt/lt/sgt/etc...)
  We compare both the low bits and high bits, and if the high bits are
  equal we return the result of the unsigned comparision on the low bits

As with other i128 ops, we are still missing immlogic support.
2021-06-09 23:02:55 +01:00
Afonso Bordado
4d085d8fbf aarch64: Add sbcs instruction encodings 2021-06-09 22:56:39 +01:00
Afonso Bordado
61f07d79a7 aarch64: Add adcs instruction encodings 2021-06-09 22:56:39 +01:00
Afonso Bordado
b1475f32a6 aarch64: Add ishl,ushr,sshr for i128 values 2021-06-09 22:48:14 +01:00
Afonso Bordado
2c4d1c0003 aarch64: Add ands instruction encoding 2021-06-09 22:38:01 +01:00
Afonso Bordado
c38a5e8b62 aarch64: Add basic i128 bit ops to the AArch64 backend
Currently we just basically use a two instruction version of the same i64 ops.
IMMLogic doesn't really support multiple register inputs, so its left as a TODO for future optimizations.
2021-06-09 22:37:55 +01:00
Chris Fallin
59ebe4fa57 Merge pull request #2964 from afonso360/merge-runtests
cranelift: Merge all run tests into runtests dir
2021-06-09 12:26:45 -07:00
Alex Crichton
e8b8947956 Bump to 0.28.0 (#2972) 2021-06-09 14:00:13 -05:00
bjorn3
e6f399419c Atomic hotswapping in JIT mode (#2786)
* Introduce new_got_entry and new_plt_entry functions

* Return NonNull<*const u8> from get_got_address

* Make GOT entry writes atomic

* Defer GOT updates until relocations and protection

Co-authored-by: Alan Egerton <eggyal@gmail.com>
2021-06-09 09:51:11 -07:00