Commit Graph

462 Commits

Author SHA1 Message Date
Dan Gohman
b4528beaf5 Bump version to 0.51.0 (#1250) 2019-11-20 22:40:55 -08:00
bjorn3
c5e74986e1 Legalize uextend and sextend to 128bit ints 2019-11-19 14:42:21 -08:00
Andrew Brown
91d29c09d0 Add x86 SIMD floating-point absolute value 2019-11-15 13:45:25 -08:00
Andrew Brown
1f17e35e95 Add x86 SIMD immediate shifts 2019-11-15 13:45:25 -08:00
Andrew Brown
6519a43b08 Add x86 SIMD floating-point negation 2019-11-15 13:45:25 -08:00
krk
f7c7245b06 Add legalization for popcnt.i128 via narrowing, fixes #1116 2019-11-15 14:03:49 +01:00
Sean Stangl
f8ae622003 Use a struct interface for creating and reading encoding bits on x86. #1156 (#1212) 2019-11-13 18:01:13 -07:00
Andrew Brown
215884e907 Simplify variable name: change inst_ to inst 2019-11-12 17:05:39 -08:00
Andrew Brown
c8eb4e9612 Add x86 SIMD floating-point arithmetic 2019-11-12 17:05:39 -08:00
Andrew Brown
04db2a9f39 Bind constant vectors to vconst; fixes #1052 (#1217) 2019-11-12 15:57:59 -08:00
Benjamin Bouvier
9080a02e10 Replace CraneStation by bytecodealliance everywhere; (#1221) 2019-11-12 10:09:31 -08:00
Andrew Brown
d32301854d Add x86 SIMD implementation of float comparison 2019-11-08 14:06:53 -08:00
Dan Gohman
cf82863ea9 Bump version to 0.49.0 (#1208) 2019-11-06 14:38:46 -08:00
Andrew Brown
af4637aff6 Add x86 SIMD legalizations for icmp less-than 2019-11-05 16:42:34 -08:00
Andrew Brown
feffed85d2 Add x86 SIMD legalizations for integer greater-than
This includes `icmp ugt`, `icmp sge`, and `icmp uge` for vectors with lanes of I8, I16, and I32.
2019-11-05 16:42:34 -08:00
Andrew Brown
0ab5760fd7 Add x86 SIMD instructions for min and max
Only the I8, I16, and I32 versions are included since Cranelift lacks support for AVX.
2019-11-05 16:42:34 -08:00
Andrew Brown
c454c3c771 Add x86 SIMD encoding for icmp sgt 2019-11-05 16:42:34 -08:00
Andrew Brown
e3a20d67b2 Add x86 SIMD legalization of icmp ne 2019-11-05 16:42:34 -08:00
Nick Fitzgerald
a49483408c Many multi-value returns (#1147)
* Add x86 encodings for `bint` converting to `i8` and `i16`

* Introduce tests for many multi-value returns

* Support arbitrary numbers of return values

This commit implements support for returning an arbitrary number of return
values from a function. During legalization we transform multi-value signatures
to take a struct return ("sret") return pointer, instead of returning its values
in registers. Callers allocate the sret space in their stack frame and pass a
pointer to it into the caller, and once the caller returns to them, they load
the return values back out of the sret stack slot. The callee's return
operations are legalized to store the return values through the given sret
pointer.

* Keep track of old, pre-legalized signatures

When legalizing a call or return for its new legalized signature, we may need to
look at the old signature in order to figure out how to legalize the call or
return.

* Add test for multi-value returns and `call_indirect`

* Encode bool -> int x86 instructions in a loop

* Rename `Signature::uses_sret` to `Signature::uses_struct_return_param`

* Rename `p` to `param`

* Add a clarifiying comment in `num_registers_required`

* Rename `num_registers_required` to `num_return_registers_required`

* Re-add newline

* Handle already-assigned parameters in `num_return_registers_required`

* Document what some debug assertions are checking for

* Make "illegalizing" closure's control flow simpler

* Add unit tests and comments for our rounding-up-to-the-next-multiple-of-a-power-of-2 function

* Use `append_isnt_arg` instead of doing the same thing  manually

* Fix grammar in comment

* Add `Signature::uses_special_{param,return}` helper functions

* Inline the definition of `legalize_type_for_sret_load` for readability

* Move sret legalization debug assertions out into their own function

* Add `round_up_to_multiple_of_type_align` helper for readability

* Add a debug assertion that we aren't removing the wrong return value

* Rename `RetPtr` stack slots to `StructReturnSlot`

* Make `legalize_type_for_sret_store` more symmetrical to `legalized_type_for_sret`

* rustfmt

* Remove unnecessary loop labels

* Do not pre-assign offsets to struct return stack slots

Instead, let the existing frame layout algorithm decide where they should go.

* Expand "sret" into explicit "struct return" in doc comment

* typo: "than" -> "then" in comment

* Fold test's debug message into the assertion itself
2019-11-05 14:36:03 -08:00
Dan Gohman
45fb377457 Bump version to 0.48.0 (#1202)
* Bump version to 0.48.0

* Re-enable `byteorder`'s default features.

The code uses `WriteBytesExt` which depends on the `std` feature being
enabled. So for now, just enable `std`.
2019-11-05 13:59:19 -08:00
Dan Gohman
a9868de3d8 Bump version to 0.47.0 2019-11-04 15:43:27 -08:00
Andrew Brown
96f5a6b561 Fix documentation link issues 2019-10-31 09:35:08 -07:00
Andrew Brown
f19456640c Add documentation for top-level items in cranelift-codegen/meta 2019-10-31 09:35:08 -07:00
Andrew Brown
e45c283194 Enable documentation of private items in cranelift-codegen/meta; fixes #832 2019-10-31 09:35:08 -07:00
Benjamin Bouvier
d8b840d2f5 [meta] Remove the OperandKindBuilder;
And replace it by constructors in OperandKind. There's a single optional
parameter function `set_doc` that remains, and didn't justify the whole
OperandKindBuilder concept to exist.
2019-10-30 18:39:20 +01:00
Benjamin Bouvier
d5e990220e [meta] Remove OperandKind::name field and explicitly pass rust_field_name/rust_type; (fixes #1177) 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
0eb2dfc4a3 [meta] Rename OperandKind::default_member to format_field_name; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
4f5b0689f3 [meta] Remove OperandKind::imm_name method; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
ae3ea47dbd [meta] Delegate finding the default value to OperandKind instead of its builder.
This applies both to the default_member value (which is now determined at
runtime, instead of pre-computed) and the rust_type value (which is
determined in the Operand's ctor, instead of the builder).
2019-10-30 18:39:20 +01:00
Benjamin Bouvier
4632d35196 [meta] Remove the OperandBuilder, replace it with Operand ctors; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
2bebc40c16 [meta] Move the doc() default values in the Operand/OperandKind; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
0b8a579943 Fixes #851: Document instructions' input operands in InstBuilder; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
e8c03fbd09 [meta] Remove unused bit-vector functionalty;
It can be resurrected if needed in the future. It was used only for the
semantics descriptions, which went away with the transition of the
meta-language to Rust.
2019-10-29 14:23:10 +01:00
Benjamin Bouvier
5889dd2c64 [meta] Add more pub(crate) definitions. 2019-10-29 14:23:10 +01:00
Benjamin Bouvier
06b1817d89 [meta] Rename Operand::is_pure_immediate into is_immediate; 2019-10-29 14:23:10 +01:00
Benjamin Bouvier
b657aa57f6 [meta] Rename Operand::is_immediate to is_immediate_or_entityref 2019-10-29 14:23:10 +01:00
Andrew Brown
f37d1c7ecc Simplify binding of IntCC::Equals to SIMD icmp; fixes #1150 2019-10-28 11:09:37 -07:00
Peter Huene
9f506692c2 Fix clippy warnings.
This commit fixes the current set of (stable) clippy warnings in the repo.
2019-10-24 17:20:12 -07:00
yjh
1176e4f178 Fix clippy warnings (#1168) 2019-10-24 09:54:31 -06:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
2019-10-22 11:01:05 -07:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats;
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
9e9a7626d7 [meta] Use a ref-counted pointer to an InstructionFormat in instructions;
This avoids a lot of dereferences, and InstructionFormat are immutable
once they're created. It removes a lot of code that was keeping the
FormatRegistry around, just in case we needed the format. This is more
in line with the way we create Instructions, and make it easy to
reference InstructionFormats in general.
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
8fece43aa1 [meta] Use a type alias for Instruction;
... instead of embedding a Rc<InstructionContent>, just make it a type
alias.
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d102bf9b61 Add allow(dead_code) for Immediate until it's used in legalization patterns; (#1157) 2019-10-18 08:05:01 -06:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
8f74333662 Add x86 SIMD band_not 2019-10-17 15:49:29 -07:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
2019-10-15 15:51:50 -07:00