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ca99bd1641e89dc87fd3c382ff9e048c8e7f57b9
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16 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
ca99bd1641 Add RISC-V regmove encodings. 2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
e15c332471 Encode iconst.i32 for RISC-V. 
For large constants with the low 12 bits clear, we already have the
"lui" encoding. Add "addi %x0" encodings for signed 12-bit constants.
 2017-06-22 12:13:37 -07:00
Jakob Stoklund Olesen
4503306f0e Add RISC-V encodings for call_indirect. 2017-06-14 16:14:16 -07:00
Jakob Stoklund Olesen
3e1e2b6e5e Add RISC-V encodings for copy instructions. 2017-06-14 15:36:25 -07:00
Jakob Stoklund Olesen
5336bbd4cc Add RISC-V encodings for spill and fill. 
Add a Stack() class for specifying operand constraints for values on the
stack.

Add encoding recipes for RISC-V spill and fill instructions. Don't
implement the encoding recipe functions yet since we don't have the
stack slot layout yet.
 2017-06-13 13:39:52 -07:00
Jakob Stoklund Olesen
0cb36c9031 Remove the return_reg instruction. 
RISC architectures that take a return address in a register can use a
special-purpose `link` return value to do so.
 2017-04-19 16:08:16 -07:00
Jakob Stoklund Olesen
4ee519e620 Add RISC-V call instruction encodings. 
Calls are jal with a fixed %x1 link register.
 2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V. 
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
 2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz. 
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
 2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
377550b835 Add return_reg encodings for RISC-V. 2017-02-21 16:29:23 -08:00
Jakob Stoklund Olesen
0b9b956695 Split out instruction definitions. 
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
 2016-11-08 12:33:50 -08:00
Jakob Stoklund Olesen
af6355e2ef Move the 'meta' dir to 'lib/cretonne/meta'. 
The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.

This is in preparation for publishing crates on crates.io.
 2016-10-17 14:19:23 -07:00