5336bbd4cc
Add a Stack() class for specifying operand constraints for values on the stack. Add encoding recipes for RISC-V spill and fill instructions. Don't implement the encoding recipe functions yet since we don't have the stack slot layout yet.
126 lines
4.5 KiB
Python
126 lines
4.5 KiB
Python
"""
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RISC-V Encodings.
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"""
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from __future__ import absolute_import
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from base import instructions as base
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from base.immediates import intcc
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from .defs import RV32, RV64
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from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
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from .recipes import LOAD, STORE
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from .recipes import R, Rshamt, Ricmp, I, Iicmp, Iret
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from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi
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from .settings import use_m
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from cdsl.ast import Var
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# Dummies for instruction predicates.
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x = Var('x')
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y = Var('y')
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dest = Var('dest')
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args = Var('args')
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# Basic arithmetic binary instructions are encoded in an R-type instruction.
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for inst, inst_imm, f3, f7 in [
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(base.iadd, base.iadd_imm, 0b000, 0b0000000),
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(base.isub, None, 0b000, 0b0100000),
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(base.bxor, base.bxor_imm, 0b100, 0b0000000),
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(base.bor, base.bor_imm, 0b110, 0b0000000),
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(base.band, base.band_imm, 0b111, 0b0000000)
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]:
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RV32.enc(inst.i32, R, OP(f3, f7))
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RV64.enc(inst.i64, R, OP(f3, f7))
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# Immediate versions for add/xor/or/and.
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if inst_imm:
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RV32.enc(inst_imm.i32, I, OPIMM(f3))
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RV64.enc(inst_imm.i64, I, OPIMM(f3))
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# 32-bit ops in RV64.
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RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
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RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
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# There are no andiw/oriw/xoriw variations.
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RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))
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# Dynamic shifts have the same masking semantics as the cton base instructions.
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for inst, inst_imm, f3, f7 in [
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(base.ishl, base.ishl_imm, 0b001, 0b0000000),
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(base.ushr, base.ushr_imm, 0b101, 0b0000000),
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(base.sshr, base.sshr_imm, 0b101, 0b0100000),
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]:
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RV32.enc(inst.i32.i32, R, OP(f3, f7))
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RV64.enc(inst.i64.i64, R, OP(f3, f7))
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RV64.enc(inst.i32.i32, R, OP32(f3, f7))
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# Allow i32 shift amounts in 64-bit shifts.
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RV64.enc(inst.i64.i32, R, OP(f3, f7))
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RV64.enc(inst.i32.i64, R, OP32(f3, f7))
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# Immediate shifts.
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RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
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RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
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RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
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# Signed and unsigned integer 'less than'. There are no 'w' variants for
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# comparing 32-bit numbers in RV64.
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RV32.enc(base.icmp.i32(intcc.slt, x, y), Ricmp, OP(0b010, 0b0000000))
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RV64.enc(base.icmp.i64(intcc.slt, x, y), Ricmp, OP(0b010, 0b0000000))
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RV32.enc(base.icmp.i32(intcc.ult, x, y), Ricmp, OP(0b011, 0b0000000))
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RV64.enc(base.icmp.i64(intcc.ult, x, y), Ricmp, OP(0b011, 0b0000000))
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RV32.enc(base.icmp_imm.i32(intcc.slt, x, y), Iicmp, OPIMM(0b010))
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RV64.enc(base.icmp_imm.i64(intcc.slt, x, y), Iicmp, OPIMM(0b010))
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RV32.enc(base.icmp_imm.i32(intcc.ult, x, y), Iicmp, OPIMM(0b011))
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RV64.enc(base.icmp_imm.i64(intcc.ult, x, y), Iicmp, OPIMM(0b011))
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# Integer constants with the low 12 bits clear are materialized by lui.
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RV32.enc(base.iconst.i32, U, LUI())
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RV64.enc(base.iconst.i32, U, LUI())
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RV64.enc(base.iconst.i64, U, LUI())
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# "M" Standard Extension for Integer Multiplication and Division.
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# Gated by the `use_m` flag.
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RV32.enc(base.imul.i32, R, OP(0b000, 0b0000001), isap=use_m)
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RV64.enc(base.imul.i64, R, OP(0b000, 0b0000001), isap=use_m)
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RV64.enc(base.imul.i32, R, OP32(0b000, 0b0000001), isap=use_m)
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# Control flow.
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# Unconditional branches.
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RV32.enc(base.jump, UJ, JAL())
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RV64.enc(base.jump, UJ, JAL())
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RV32.enc(base.call, UJcall, JAL())
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RV64.enc(base.call, UJcall, JAL())
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# Conditional branches.
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for cond, f3 in [
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(intcc.eq, 0b000),
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(intcc.ne, 0b001),
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(intcc.slt, 0b100),
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(intcc.sge, 0b101),
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(intcc.ult, 0b110),
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(intcc.uge, 0b111)
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]:
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RV32.enc(base.br_icmp.i32(cond, x, y, dest, args), SB, BRANCH(f3))
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RV64.enc(base.br_icmp.i64(cond, x, y, dest, args), SB, BRANCH(f3))
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for inst, f3 in [
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(base.brz, 0b000),
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(base.brnz, 0b001)
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]:
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RV32.enc(inst.i32, SBzero, BRANCH(f3))
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RV64.enc(inst.i64, SBzero, BRANCH(f3))
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RV32.enc(inst.b1, SBzero, BRANCH(f3))
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RV64.enc(inst.b1, SBzero, BRANCH(f3))
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# Returns are a special case of JALR using %x1 to hold the return address.
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# The return address is provided by a special-purpose `link` return value that
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# is added by legalize_signature().
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RV32.enc(base.x_return, Iret, JALR())
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RV64.enc(base.x_return, Iret, JALR())
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# Spill and fill.
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RV32.enc(base.spill.i32, GPsp, STORE(0b010))
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RV64.enc(base.spill.i32, GPsp, STORE(0b010))
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RV64.enc(base.spill.i64, GPsp, STORE(0b011))
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RV32.enc(base.fill.i32, GPfi, LOAD(0b010))
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RV64.enc(base.fill.i32, GPfi, LOAD(0b010))
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RV64.enc(base.fill.i64, GPfi, LOAD(0b011))
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