Commit Graph

7138 Commits

Author SHA1 Message Date
Andrew Brown
c8cce5d2d7 [machinst x64]: enable packed saturated arithmetic 2020-10-08 08:46:20 -07:00
Benjamin Bouvier
116acb8dcd machinst x64: emit nop of variable sizes; 2020-10-08 10:05:57 +02:00
Benjamin Bouvier
a470f1e0cd machinst x64: remove dead code and allow(dead_code) annotation;
The BranchTarget is always used as a label, so just use a plain
MachLabel in this case.
2020-10-08 10:05:57 +02:00
Benjamin Bouvier
e32e6fb612 machinst x64: check SSE requirements for instructions against enabled features; 2020-10-08 09:21:51 +02:00
Benjamin Bouvier
c5bbc87498 machinst: allow passing constant information to the instruction emitter;
A new associated type Info is added to MachInstEmit, which is the
immutable counterpart to State. It can't easily be constructed from an
ABICallee, since it would require adding an associated type to the
latter, and making so leaks the associated type in a lot of places in
the code base and makes the code harder to read. Instead, the EmitInfo
state can simply be passed to the `Vcode::emit` function directly.
2020-10-08 09:21:51 +02:00
Andrew Brown
3778fa025c Switch DataValue to use Ieee32/Ieee64
As discussed in #2251, in order to be very confident that NaN signaling bits are correctly handled by the compiler, this switches `DataValue` to use Cranelift's `Ieee32` and `Ieee64` structures. This makes it a bit more inconvenient to interpreter Cranelift FP operations but this should change to something like `rustc_apfloat` in the future.
2020-10-07 12:17:17 -07:00
Andrew Brown
ce44719e1f refactor: change LowerCtx::get_immediate to return a DataValue
This change abstracts away (from the perspective of the new backend) how immediate values are stored in InstructionData. It gathers large immediates from necessary places (e.g. constant pool) and delegates to `InstructionData::imm_value` for the rest. This refactor only touches original users of `LowerCtx::get_immediate` but a future change could do the same for any place the new backend is accessing InstructionData directly to retrieve immediates.
2020-10-07 12:17:17 -07:00
Andrew Brown
3a2025fdc7 Add InstructionData::imm_value() 2020-10-07 12:17:17 -07:00
Andrew Brown
6f6f79ef2b refactor: move DataValue from cranelift-reader to cranelift-codegen
This is no change to functionality; the move is necessary in order to return InstructionData immediates in a structure way (see next commit).
2020-10-07 12:17:17 -07:00
Gabor Greif
387afc805e debug: Normalise value prior to right shifts (#2276)
* normalise value prior to right shifts

by first left-aligning (shift left by 32 bits)
then shifting back (respecting signedness)

* Update crates/debug/src/transform/expression.rs

Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>

* Update crates/debug/src/transform/expression.rs

* Update crates/debug/src/transform/expression.rs

* update translation of DW_OP_shr in test

* add translation test for DW_OP_shra

* explain normalisation

* optimise the expression by performing only one right shift

We assume that the expression evaluator permits collapsing
two shifts as long as they go in the same direction.

Review feedback.

Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
2020-10-07 12:42:20 -05:00
subtly
d91f0c3933 get pc for freebsd (#2270)
* get pc for freebsd

* whitespace :|

* fix; i386 to x86

* remove x86 since uc_mcontext isn't yet in libc

* freebsd build of rust uses libcc/unwind
2020-10-07 06:30:14 -05:00
Benjamin Bouvier
84ac3feef8 machinst x64: use zero-latency move instructions for f32/f64;
As found by @julian-seward1, movss/movsd aren't included in the
zero-latency move instructions section of the Intel optimization manual.
Use MOVAPS instead for those moves.
2020-10-07 10:55:44 +02:00
Chris Fallin
fc430eef76 Merge pull request #2267 from cfallin/fix-aarch64-abi
Fix AArch64 ABI to respect half-caller-save, half-callee-save vec regs.
2020-10-06 15:42:51 -07:00
Chris Fallin
71768bb6cf Fix AArch64 ABI to respect half-caller-save, half-callee-save vec regs.
This PR updates the AArch64 ABI implementation so that it (i) properly
respects that v8-v15 inclusive have callee-save lower halves, and
caller-save upper halves, by conservatively approximating (to full
registers) in the appropriate directions when generating prologue
caller-saves and when informing the regalloc of clobbered regs across
callsites.

In order to prevent saving all of these vector registers in the prologue
of every non-leaf function due to the above approximation, this also
makes use of a new regalloc.rs feature to exclude call instructions'
writes from the clobber set returned by register allocation. This is
safe whenever the caller and callee have the same ABI (because anything
the callee could clobber, the caller is allowed to clobber as well
without saving it in the prologue).

Fixes #2254.
2020-10-06 14:44:02 -07:00
Alex Crichton
e22e2c3722 Update Github Actions CI set-env/add-path (#2265)
In accordance with [this
advisory](https://github.blog/changelog/2020-10-01-github-actions-deprecating-set-env-and-add-path-commands/)
it's recommended we moved to a different scheme of setting env vars and
updating PATH.
2020-10-05 15:08:56 -05:00
Alex Crichton
9e87e45745 Update wasmparser, wast, and spec test suite (#2264)
This brings in a number of SIMD opcode renames, various other test suite
updates, as well as some new proposed SIMD opcodes too.
2020-10-05 13:51:16 -05:00
zhiqiangxu
1d1de35ad1 optimize register_jit_code (#2262) 2020-10-05 13:14:44 -05:00
Alex Crichton
2c6841041d Validate modules while translating (#2059)
* Validate modules while translating

This commit is a change to cranelift-wasm to validate each function body
as it is translated. Additionally top-level module translation functions
will perform module validation. This commit builds on changes in
wasmparser to perform module validation interwtwined with parsing and
translation. This will be necessary for future wasm features such as
module linking where the type behind a function index, for example, can
be far away in another module. Additionally this also brings a nice
benefit where parsing the binary only happens once (instead of having an
up-front serial validation step) and validation can happen in parallel
for each function.

Most of the changes in this commit are plumbing to make sure everything
lines up right. The major functional change here is that module
compilation should be faster by validating in parallel (or skipping
function validation entirely in the case of a cache hit). Otherwise from
a user-facing perspective nothing should be that different.

This commit does mean that cranelift's translation now inherently
validates the input wasm module. This means that the Spidermonkey
integration of cranelift-wasm will also be validating the function as
it's being translated with cranelift. The associated PR for wasmparser
(bytecodealliance/wasmparser#62) provides the necessary tools to create
a `FuncValidator` for Gecko, but this is something I'll want careful
review for before landing!

* Read function operators until EOF

This way we can let the validator take care of any issues with
mismatched `end` instructions and/or trailing operators/bytes.
2020-10-05 11:02:01 -05:00
Benjamin Bouvier
df8f85f4bc machinst x64: remove non_camel_case_types; 2020-10-05 17:44:31 +02:00
Benjamin Bouvier
4a10a78e33 machinst x64: remove non_snake_case; 2020-10-05 17:44:31 +02:00
Johnnie Birch
5799fd3cc0 Add file test simd-arithmetic-run to x64 backend
Copies over simd-arithmetic-run from the old backend, adding
several run tests including for min/max. Tests not supported
are commented out.
2020-10-02 16:20:10 -07:00
Johnnie Birch
7b4d173b90 Adds packed floating point min/max for X64 for the new backend
Allows for simd_f32x4 and simd_f64x2 spec tests
2020-10-02 16:20:10 -07:00
Chris Fallin
cf6e5e71cd Merge pull request #2260 from cfallin/arm32-compile-ci
Add ARM32 build test to CI.
2020-10-02 13:25:19 -07:00
Chris Fallin
e71d4fdbb8 Add ARM32 build test to CI.
We do not yet want to gate our CI on tests passing, because the backend
is only partially complete; but we want to make sure that it remains
up-to-date as we change internal APIs.
2020-10-02 12:48:22 -07:00
Chris Fallin
57fed69792 Merge pull request #2259 from cfallin/fix-arm32-build
Fix arm32 build after some ABI framework changes.
2020-10-02 12:34:57 -07:00
Chris Fallin
3ca173e4bc Fix arm32 build after some ABI framework changes.
It turns out that while we don't have the partial/experimental arm32
backend tested on our CI yet, the Firefox build *does* at least rely on
the backend to build, because it specifies the `arm32` feature to
`cranelift-codegen`, even if it will never invoke the backend.
Our previous old-framework arm32 stub at least compiled, so it didn't
break Firefox.

We should probably add a CI build check to ensure we don't bitrot what
we have here, but this is the immediate fix to get us back to sanity.
2020-10-02 11:55:46 -07:00
Chris Fallin
b2f52910fb Merge pull request #2224 from jgouly/sp_adjust
arm64: Use SignedOffset rather than PreIndexed addressing mode for ca…
2020-10-02 09:18:00 -07:00
Andrew Brown
ca1b76421a [machinst x64]: remove duplicate code to insert a lane 2020-10-02 08:29:31 -07:00
Andrew Brown
c42a097a0c [machinst x64]: use is64 instead of w_bit 2020-10-02 08:29:31 -07:00
Andrew Brown
16a2538ecd [machinst x64]: rename Inst::XmmUninitializedValue and document
This approach is not the best but avoids an extra instruction; perhaps at some point, as mentioned in https://github.com/bytecodealliance/wasmtime/pull/2248, we will add the extra instruction or refactor things in such a way that this `Inst` variant is unnecessary.
2020-10-02 08:29:31 -07:00
Andrew Brown
3d9f3bf728 [machinst x64]: port CLIF tests related to comparison and lane operations 2020-10-02 08:29:31 -07:00
Andrew Brown
a82d1604cb [machinst x64]: enable lane spec tests 2020-10-02 08:29:31 -07:00
Andrew Brown
50b9399006 [machinst x64]: lower remaining lane operations--any_true, all_true, splat 2020-10-02 08:29:31 -07:00
Andrew Brown
4565582f02 [machinst x64]: clarify parameter name of Inst::xmm_rm_r_imm 2020-10-02 08:29:31 -07:00
Andrew Brown
0579e9f9de [machinst x64]: add packed OR 2020-10-02 08:29:31 -07:00
Andrew Brown
f6bfa71dc1 [machinst x64]: enable integer comparison SIMD spec tests 2020-10-02 08:29:31 -07:00
Andrew Brown
74226d6781 [machinst x64]: add integer comparisons 2020-10-02 08:29:31 -07:00
Joey Gouly
eec60c9b06 arm64: Use SignedOffset rather than PreIndexed addressing mode for callee-saved registers
This also passes `fixed_frame_storage_size` (previously `total_sp_adjust`)
into `gen_clobber_save` so that it can be combined with other stack
adjustments.

Copyright (c) 2020, Arm Limited.
2020-10-02 16:22:55 +01:00
Benjamin Bouvier
d7fda6ac0e Update subscribe-to-label.json 2020-10-02 10:18:25 +02:00
Chris Fallin
5c1d728e3a Merge pull request #2228 from akirilov-arm/vector_callee_saves
AArch64: Add test cases for callee-saved SIMD & FP registers
2020-10-01 17:08:33 -07:00
Nick Fitzgerald
81ce92b7ef Add reminder to tag releases to publish script (#2250) 2020-09-30 17:37:29 -05:00
Chris Fallin
b8f0dc429f Merge pull request #2223 from cfallin/baldrdash-2020
Support for SpiderMonkey's "Wasm ABI 2020" in general and on AArch64.
2020-09-30 15:33:05 -07:00
Chris Fallin
835db11bea Support for SpiderMonkey's "Wasm ABI 2020".
As part of a Wasm JIT update, SpiderMonkey is changing its internal
WebAssembly function ABI. The new ABI's frame format includes "caller
TLS" and "callee TLS" slots. The details of where these come from are
not important; from Cranelift's point of view, the only relevant
requirement is that we have two on-stack args that are always present
(offsetting other on-stack args), and that we define special argument
purposes so that we can supply values for these slots.

Note that this adds a *new* ABI (a variant of the Baldrdash ABI) because
we do not want to tightly couple the landing of this PR to the landing
of the changes in SpiderMonkey; it's better if both the old and new
behavior remain available in Cranelift, so SpiderMonkey can continue to
vendor Cranelift even if it does not land (or backs out) the ABI change.

Furthermore, note that this needs to be a Cranelift-level change (i.e.
cannot be done purely from the translator environment implementation)
because the special TLS arguments must always go on the stack, which
would not otherwise happen with the usual argument-placement logic; and
there is no primitive to push a value directly in CLIF code (the notion
of a stack frame is a lower-level concept).
2020-09-30 14:55:56 -07:00
Anton Kirilov
d18de69e5a AArch64: Add test cases for callee-saved SIMD & FP registers
Copyright (c) 2020, Arm Limited.
2020-09-30 14:19:02 +01:00
Alex Crichton
a04001211c Add metadata to peepmatic crates (#2245) 2020-09-29 18:56:08 -05:00
Andrew Brown
4484a00ea5 [machinst x64]: calculate extension modes in one place 2020-09-29 14:48:59 -07:00
Joshua Warner
eb650f6fe0 filesystem example (#2236) 2020-09-29 13:20:14 -05:00
Andrew Brown
715be68101 [machinst x64]: assert lane is correct size for extractlane
This change applies a good suggestion @bjorn3 made in #2230 that I forgot to implement there.
2020-09-29 09:34:22 -07:00
Andrew Brown
b43f4a464a refactor: move all 'filetests/vcode' tests to 'filetests/isa' 2020-09-29 09:27:39 -07:00
Andrew Brown
452d854855 [machinst x64]: demonstrate that packed register moves are elided 2020-09-29 08:48:37 -07:00