Commit Graph

5 Commits

Author SHA1 Message Date
Dan Gohman
b8a106adf0 Remove the "has_sse2" flag.
Cretonne currently requires SSE2 support pervasively, so it's not meaningful
to have a setting for it.
2018-03-12 12:38:01 -07:00
Julian Seward
6f8a54b6a5 Adds support for legalizing CLZ, CTZ and POPCOUNT on baseline x86_64 targets.
Changes:

* Adds a new generic instruction, SELECTIF, that does value selection (a la
  conditional move) similarly to existing SELECT, except that it is
  controlled by condition code input and flags-register inputs.

* Adds a new Intel x86_64 variant, 'baseline', that supports SSE2 and
  nothing else.

* Adds new Intel x86_64 instructions BSR and BSF.

* Implements generic CLZ, CTZ and POPCOUNT on x86_64 'baseline' targets
  using the new BSR, BSF and SELECTIF instructions.

* Implements SELECTIF on x86_64 targets using conditional-moves.

* new test filetests/isa/intel/baseline_clz_ctz_popcount.cton
  (for legalization)

* new test filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton
  (for encoding)

* Allow lib/cretonne/meta/gen_legalizer.py to generate non-snake-caseified
  Rust without rustc complaining.

Fixes #238.
2018-02-06 09:43:00 -08:00
Jakob Stoklund Olesen
f91d747bda Add support for setting presets.
Fixes #11.

Presets are groups of settings and values applied at once. This is used
as a shorthand in test files, so for example "isa intel nehalem" enables
all of the CPUID bits that the Nehalem micro-architecture provides.
2017-07-14 13:57:44 -07:00
Jakob Stoklund Olesen
5cbcd59cf0 Add some ISA predicates for Intel CPUID features.
Guard the popcnt instruction on the proper CPUID bits.
2017-07-12 16:05:20 -07:00
Jakob Stoklund Olesen
fb4db38dd6 Fill in boilerplate for Intel and ARM targets.
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
2016-11-23 10:42:07 -08:00