Commit Graph

10 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
997919c696 Add encodings for imul instructions to RISC-V.
This is just the basic 'imul' the M instruction set also has mulh/mulhu which
yield the high bits of a multiplication, and there are div/rem instructions to
be implemented.

These instructions are gated by the use_m predicate, but ISA predicates are not
completely implemented yet.
2016-08-30 16:16:28 -07:00
Jakob Stoklund Olesen
09734f2033 Add controls for enabling M, F, and D RISC-V extensions.
Three predicates affect each extension:

- supports_m determines whether the target CPU supports the instruction set.
- enable_m determines if the instructions should be used, assuming they're
  available.
- use_m is the predicate used to actually use the instructions.
2016-08-30 15:44:26 -07:00
Jakob Stoklund Olesen
a21935a5a2 Add 32-bit ops to RV64.
The 32-bit arithmetic instructions are encoded differently in the RISC-V 64-bit
mode.
2016-08-26 16:13:22 -07:00
Jakob Stoklund Olesen
c1ae0c99ed Move predicate collection into TargetISA.
Add a TargetISA.finish() method which computes derived data structures after
the ISA definitions have been loaded.
2016-08-26 09:37:05 -07:00
Jakob Stoklund Olesen
586fbbc797 Add RISC-V arithmetic w/immediate operand encodings.
Add new instruction predicates to support the 'I' encoding recipe: IsSignedInt,
IsUnsignedInt used to test that an immediate operand is in the allowed range.
2016-08-24 08:53:44 -07:00
Jakob Stoklund Olesen
9da6847805 Python 3 compat.
Try to keep our Python sources compatible with both Python 2.7 and 3.

Check with 'pylint --py3k' and 'python -3'.
2016-08-23 16:35:58 -07:00
Jakob Stoklund Olesen
24870f0db9 Add RISC-V encodings for imediate shifts.
Also add the 32-bit shift instructions for RV64.
2016-08-19 15:56:09 -07:00
Jakob Stoklund Olesen
13d33d5a7a Introduce predicates.
Predcates are boolean functions. There will be ISA predicates and instruction
predicates.

The ISA predicates will be turned into member functions on the generated Flags
structs.
2016-08-11 16:40:54 -07:00
Jakob Stoklund Olesen
4efb0efb44 Add ISA-dependent settings for RISC-V. 2016-08-05 16:19:46 -07:00
Jakob Stoklund Olesen
1a4d07d437 Rename meta/target -> meta/isa.
Clarify terminology by always referring to a 'Target ISA' instead of just
'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python
code.

This is only to clarify terminology and not at all because Cargo insists on
using the 'target' sub-directory for build products. Oh, no. Not at all.
2016-08-04 11:50:19 -07:00