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ae926157c29c900621b2e98d07a742a7ab32b67a
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4 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
ae926157c2 Generate register class descriptors. 
Add a mechanism for defining sub-classes of register classes.
 2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
19ac05577c Fill in boilerplate for Intel and ARM targets. 
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
 2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen
4192ba0532 Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
b0b6a8f693 Define register banks. 
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
 2016-11-11 14:17:10 -08:00