Commit Graph

8918 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
b4ac520332 Extending loads and truncating stores 2017-04-11 10:30:03 -07:00
Jakob Stoklund Olesen
ca448d4ede Extending loads and truncating stores 2017-04-11 10:30:03 -07:00
Jakob Stoklund Olesen
aad6ebebb5 Add load and store instructions.
Define a MemFlags class, currently holding a notrap and aligned flag.
2017-04-11 09:54:55 -07:00
Jakob Stoklund Olesen
9d9807688c Add load and store instructions.
Define a MemFlags class, currently holding a notrap and aligned flag.
2017-04-11 09:54:55 -07:00
Jakob Stoklund Olesen
0c3771bccb Ensure that the docs examples verify as Cretonne IL.
Any *.cton files in the docs directory are now included when running the
test-all.sh script. This is to ensure that the examples are in fact
correct IL.

Always print NaN and Inf floats with a sign. Print the positive ones as
+NaN and +Inf to make them easier to parse.
2017-04-10 15:28:24 -07:00
Jakob Stoklund Olesen
46f0393417 Ensure that the docs examples verify as Cretonne IL.
Any *.cton files in the docs directory are now included when running the
test-all.sh script. This is to ensure that the examples are in fact
correct IL.

Always print NaN and Inf floats with a sign. Print the positive ones as
+NaN and +Inf to make them easier to parse.
2017-04-10 15:28:24 -07:00
Jakob Stoklund Olesen
b474485c0d Add heap_load, heap_store, and heap_addr instructions.
These are used when lowering WebAssembly sandbox code.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
b5237b6a4a Add heap_load, heap_store, and heap_addr instructions.
These are used when lowering WebAssembly sandbox code.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
e78e4ea4ec Add a Uoffset32 immediate operand kind.
WebAssembly memory instructions encode a 32-bit unsigned offset that is
used to compute an effective address.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
ca12a683ac Add a Uoffset32 immediate operand kind.
WebAssembly memory instructions encode a 32-bit unsigned offset that is
used to compute an effective address.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
222ae8af22 Define stack_load, stack_store, and stack_addr instructions. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
c52e3e0b3f Define stack_load, stack_store, and stack_addr instructions. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
7c3bc9d19f Add Offset32 support to the parser. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
af2516e996 Add Offset32 support to the parser. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
eccc2d0dae Add an Offset32 immediate operand kind.
This will be used to represent an immediate 32-bit signed address offset
for load/store instructions.
2017-04-10 11:53:46 -07:00
Jakob Stoklund Olesen
ab1e51002d Add an Offset32 immediate operand kind.
This will be used to represent an immediate 32-bit signed address offset
for load/store instructions.
2017-04-10 11:53:46 -07:00
Jakob Stoklund Olesen
51dea9f784 Syntax tweak: Omit comma after an initial enum immediate.
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
13b0046ed7 Syntax tweak: Omit comma after an initial enum immediate.
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V.
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
d2f575b54a Add jump encodings to RISC-V.
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
fa4f151b9b Add a fallthrough instruction.
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
2017-04-06 14:22:32 -07:00
Jakob Stoklund Olesen
e5e5b30315 Add a fallthrough instruction.
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
2017-04-06 14:22:32 -07:00
Jakob Stoklund Olesen
5025bb67f4 Add an iterators module with extra Iterator methods.
Start with an adjacent_pairs() iterator adapter.
2017-04-06 14:00:56 -07:00
Jakob Stoklund Olesen
c6e027207c Add an iterators module with extra Iterator methods.
Start with an adjacent_pairs() iterator adapter.
2017-04-06 14:00:56 -07:00
Jakob Stoklund Olesen
856a67ca3a Use EBB offsets for encoding RISC-V branches.
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
1440b673fc Use EBB offsets for encoding RISC-V branches.
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
8a3f538441 Fix a bug in the binemit file test.
Only emit each instruction once, or the offset computations go all
wrong.
2017-04-06 11:17:46 -07:00
Jakob Stoklund Olesen
e56482d0fd Fix a bug in the binemit file test.
Only emit each instruction once, or the offset computations go all
wrong.
2017-04-06 11:17:46 -07:00
Jakob Stoklund Olesen
81251c3005 Add a branch relaxation pass for #72.
Compute exact EBB header offsets and check that branches are in range.

Not implemented yet: Relax branches that are not in range.

Invoke the relax_branches() pass from the 'test binemit' file tests so
they can verify the proper encoding of branch instructions too.
2017-04-05 15:11:39 -07:00
Jakob Stoklund Olesen
b5c74fdc25 Add a branch relaxation pass for #72.
Compute exact EBB header offsets and check that branches are in range.

Not implemented yet: Relax branches that are not in range.

Invoke the relax_branches() pass from the 'test binemit' file tests so
they can verify the proper encoding of branch instructions too.
2017-04-05 15:11:39 -07:00
Jakob Stoklund Olesen
598c81c12e Add encoding size information to EncInfo.
Two new pieces of information are available for all encoding recipes:

- The size in bytes of an encoded instruction, and
- The range of a branch encoded with the recipe, if any.

In the meta language, EncRecipe takes two new constructor arguments. The
size is required for all encodings and branch_range is required for all
recipes used to encode branches.
2017-04-05 11:46:19 -07:00
Jakob Stoklund Olesen
eb1052718b Add encoding size information to EncInfo.
Two new pieces of information are available for all encoding recipes:

- The size in bytes of an encoded instruction, and
- The range of a branch encoded with the recipe, if any.

In the meta language, EncRecipe takes two new constructor arguments. The
size is required for all encodings and branch_range is required for all
recipes used to encode branches.
2017-04-05 11:46:19 -07:00
Jakob Stoklund Olesen
f47c62ba8c Move encoding-related information into an EncInfo struct.
The tables returned by recipe_names() and recipe_constraints() are now
collected into an EncInfo struct that is available from
TargetIsa::encoding_info(). This is equivalent to the register bank
tables available fro TargetIsa::register_info().

This cleans of the TargetIsa interface and makes it easier to add
encoding-related information.
2017-04-05 10:07:19 -07:00
Jakob Stoklund Olesen
6ab35e54b8 Move encoding-related information into an EncInfo struct.
The tables returned by recipe_names() and recipe_constraints() are now
collected into an EncInfo struct that is available from
TargetIsa::encoding_info(). This is equivalent to the register bank
tables available fro TargetIsa::register_info().

This cleans of the TargetIsa interface and makes it easier to add
encoding-related information.
2017-04-05 10:07:19 -07:00
Jakob Stoklund Olesen
72cb6459a9 Add a CodeOffset type and CodeSink::offset() method.
We need to keep track of code offsets in order to compute accurate
branch displacements.
2017-04-05 09:12:12 -07:00
Jakob Stoklund Olesen
847c8045fd Add a CodeOffset type and CodeSink::offset() method.
We need to keep track of code offsets in order to compute accurate
branch displacements.
2017-04-05 09:12:12 -07:00
Jakob Stoklund Olesen
1984c96f7c rustfmt 0.8.1 2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
8353651559 rustfmt 0.8.1 2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz.
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
3a47b40ff8 Add RISC-V encodings for brz and brnz.
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V.
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
39e102b155 Add conditional branch encodings for RISC-V.
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
1b6a6f4e48 Add the br_icmp instruction.
This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.
2017-04-03 15:04:42 -07:00
Jakob Stoklund Olesen
d2ddc700a8 Add the br_icmp instruction.
This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.
2017-04-03 15:04:42 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui.
This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
175b269760 Add RISC-V encodings for lui.
This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V.
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
c13c318ec4 Add icmp_imm encodings for RISC-V.
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
e65be4d827 Give singleton type variables the type's doc string.
This reads better than "typeof(b1)".
2017-04-03 10:06:08 -07:00
Jakob Stoklund Olesen
d4d76c8d76 Give singleton type variables the type's doc string.
This reads better than "typeof(b1)".
2017-04-03 10:06:08 -07:00