Commit Graph

12 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
00551dbc5f Add RISC-V encodings for spill and fill.
Add a Stack() class for specifying operand constraints for values on the
stack.

Add encoding recipes for RISC-V spill and fill instructions. Don't
implement the encoding recipe functions yet since we don't have the
stack slot layout yet.
2017-06-13 13:39:52 -07:00
Jakob Stoklund Olesen
09ac27a797 Compute top-level register classes for each register bank.
A top-level register class is one that has no sub-classes. It is
possible to have multiple top-level register classes in the same
register bank. For example, ARM's FPR bank has both D and Q top-level
register classes.

Number register classes such that all top-level register classes appear
as a contiguous sequence starting from 0. This will be used by the
register allocator when counting used registers per top-level register
class.
2017-05-15 15:19:49 -07:00
Jakob Stoklund Olesen
ca6eddaf88 Add a register bank index to RegClassData.
This makes it possible to find the register bank that contains a
register class.
2017-05-15 15:17:58 -07:00
Jakob Stoklund Olesen
cdb3a71dd1 Add encodings for Intel dynamic shift instructions.
These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
2017-05-09 13:11:50 -07:00
Jakob Stoklund Olesen
a82e521291 Add more mypy annotations. 2017-03-30 15:16:44 -07:00
Jakob Stoklund Olesen
8c5a69eb47 Fixed for mypy 0.501.
The List and Dict types are no longer implicitly available. They must be
imported from typing.

Type annotations must appear before the doc comment in a function. Also
fix type errors in these functions that weren't detected before.
2017-03-03 09:08:28 -08:00
Jakob Stoklund Olesen
672e4abd7e Compute register class intersections.
Ensure that the set of register classes is closed under intersection.

Provide a RegClass::intersect() method which finds the register class
representing the intersection of two classes.

Generate a bit-mask of subclasses for each register class to be used by
the intersect() method.

Ensure that register classes are sorted topologically. This is also used
by the intersect() method.
2017-01-25 13:57:43 -08:00
Jakob Stoklund Olesen
0394f35034 Add operand register constraints.
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
58dedb673a Add an AllocatableSet for registers.
This set of available register units also manages register aliasing in
an efficient way.

Detect if the units in a register straddles mask words. The algorithm
for allocating multi-unit registers expect the whole register to be
inside a single mask word. We could handle this if necessary, but so far
no ISAs need it.
2017-01-23 12:43:32 -08:00
Jakob Stoklund Olesen
ae926157c2 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
4192ba0532 Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
b0b6a8f693 Define register banks.
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
2016-11-11 14:17:10 -08:00