Commit Graph

13 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
788a78caf4 Add Intel encodings for ifcmp_sp.
Also generate an Into<RegUnit> implementation for the RU enums.
2018-02-09 14:32:29 -08:00
Tyler McMullen
eb85aa833c Illegalize rbp/r13 for zero-offset loads on Intel x64 (#225)
* Switch RegClass to a bitmap implementation.

* Add special RegClass to remove r13 from 'ld' recipe.

* Use MASK_LEN constant instead of magic number.

* Enforce that RegClass slicing is only valid on contiguous classes.

* Use Optional[int] for RegClass optional bitmask parameter.

* Add comment explaining use of Intel ISA's GPR_NORIP register class.
2018-01-16 20:05:53 -08:00
Jakob Stoklund Olesen
1dbc55dadf Add a pressure_tracking flag to register banks.
This makes it possible to define register banks that opt out of register
pressure tracking. This will be used to define banks for special-purpose
registers like the CPU flags.

The pressure tracker does not need to use resources for a top-level
register class in a non-tracked bank. The constant MAX_TOPRCS is renamed
to MAX_TRACKED_TOPRCS to indicate that there may be top-level register
classes with higher numbers, but they won't require pressure tracking.

We won't be tracking register pressure for CPU flags since only one
value is allowed to be live at a time.
2017-10-13 13:46:16 -07:00
Jakob Stoklund Olesen
ce4d723a73 Give RegClassData a reference to its parent RegInfo.
This makes it possible to materialize new RegClass references without
requiring a RegInfo reference to be passed around.

- Move the RegInfo::toprc() method to RegClassData.
- Rename RegClassData::intersect() to intersect_index() and provide a
  new intersect() which returns a register class.
- Remove some &RegInfo parameters that are no longer needed.
2017-10-04 17:02:09 -07:00
Jakob Stoklund Olesen
983048cdd1 Generate an enum with all the register units in a target.
It is sometimes useful to create constant lists of register units by
name. The generated RU enum can be used for that.
2017-06-30 10:39:51 -07:00
Jakob Stoklund Olesen
71bb7483b7 Compute top-level register classes for each register bank.
A top-level register class is one that has no sub-classes. It is
possible to have multiple top-level register classes in the same
register bank. For example, ARM's FPR bank has both D and Q top-level
register classes.

Number register classes such that all top-level register classes appear
as a contiguous sequence starting from 0. This will be used by the
register allocator when counting used registers per top-level register
class.
2017-05-15 15:19:49 -07:00
Jakob Stoklund Olesen
621f3a2f50 Add a register bank index to RegClassData.
This makes it possible to find the register bank that contains a
register class.
2017-05-15 15:17:58 -07:00
Jakob Stoklund Olesen
42e7021865 Implement legalize_signature for RISC-V.
Add an abi module with code that is probably useful to all ISAs when
implementing this function.

Add a unit() method to RegClassData which can be used to index the
register units in a class.
2017-03-03 11:09:55 -08:00
Jakob Stoklund Olesen
c01ff670ed Fixed for mypy 0.501.
The List and Dict types are no longer implicitly available. They must be
imported from typing.

Type annotations must appear before the doc comment in a function. Also
fix type errors in these functions that weren't detected before.
2017-03-03 09:08:28 -08:00
Jakob Stoklund Olesen
e60d7f179c Give register classes a name.
This is just for better error messages etc.
2017-02-16 13:57:28 -08:00
Jakob Stoklund Olesen
130c4acf51 Compute register class intersections.
Ensure that the set of register classes is closed under intersection.

Provide a RegClass::intersect() method which finds the register class
representing the intersection of two classes.

Generate a bit-mask of subclasses for each register class to be used by
the intersect() method.

Ensure that register classes are sorted topologically. This is also used
by the intersect() method.
2017-01-25 13:57:43 -08:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions.
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
2016-11-22 18:15:21 -08:00