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54 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
bd8230411a Encodings for load/store instructions. 
We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.
 2017-05-12 16:49:39 -07:00
Jakob Stoklund Olesen
f4929825ca Add subtract and logical instruction encodings to Intel-32. 
Also add versions with 8-bit and 32-bit immediate operands.
 2017-05-12 15:37:12 -07:00
Jakob Stoklund Olesen
a0085434af Add encodings for Intel dynamic shift instructions. 
These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
 2017-05-09 13:11:50 -07:00
Jakob Stoklund Olesen
041fda63ac Add the very basics of Intel 32-bit instruction encodings. 
Tabulate the Intel opcode representations and implement an OP() function
which computes the encoding bits.

Implement the single-byte opcode with a reg-reg ModR/M byte.
 2017-05-08 16:57:38 -07:00