a0085434af
These instructions have a fixed register constraint; the shift amount is passed in CL. Add meta language syntax so a fixed register can be specified as "GPR.rcx".
18 lines
533 B
Python
18 lines
533 B
Python
"""
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Intel Encodings.
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"""
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from __future__ import absolute_import
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from base import instructions as base
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from .defs import I32
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from .recipes import Op1rr, Op1rc
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from .recipes import OP
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I32.enc(base.iadd.i32, Op1rr, OP(0x01))
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# 32-bit shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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I32.enc(base.ishl.i32.i32, Op1rc, OP(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, Op1rc, OP(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, Op1rc, OP(0xd3, rrr=7))
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