Commit Graph

273 Commits

Author SHA1 Message Date
Dan Gohman
54c388d870 Make the verifier output even prettier (#599)
* Fix verifier printing to print instruction encodings consistently.

Use `FuncWriter::write_instruction` for all instructions so that
encodings are printed consistently.

* Make use-before-def errors mention the relevant value.

* When there are verifier errors, print a message at the end.

* Make verifier errors prettier.

Fix the length of the "^~~~~" to match the printed entity, and print the
error messsage on its own line.

* Clean up "test verifier" failure messages.

* Tidy the uses-value-from-itself error.

The use instruction is the same as the def instruction, so don't print
both. Also, the use instruction is already being printed at the
beginning, so don't print it again at the end.
2018-11-26 22:18:18 -08:00
Syrus Akbary
48186b3199 Make TargetIsa thread-safe 2018-11-20 22:15:40 -06:00
Dan Gohman
0fed78e063 Don't allow loop preheaders to have critical edges.
If the block which would be a preheader for a loop has other successors,
don't hoist instructions into it. Instead create a dedicated preheader.
2018-11-16 10:27:24 +01:00
Dan Gohman
641771ac6a Add encodings to the instructions in LICM's generated preheaders.
When LICM generates a preheader, it needs to add encodings to the
instructions it generates, since it runs after legalization.
2018-11-16 10:27:24 +01:00
Benjamin Bouvier
b41bc55007 Pretty-print errors for extended basic blocks too; 2018-11-14 13:08:54 -08:00
Benjamin Bouvier
d45e8b5830 Add SIB/offset for ABCD stores too; 2018-11-14 13:08:54 -08:00
Benjamin Bouvier
b170b74b65 Fixes #600: Add a SIB byte when encoding a non-indexed load/store into r12/rsp;
Memory access instructions which took the GPR_ZERO_DEREF_SAFE register
class (that was removed in #600) should check for the need of either an
offset (r13/rbp) or the SIB byte (r12/rsp). Some load/store instructions
would already take an index, thus already contain the SIB byte in this
case (see instructions which have a comment telling that the else branch
already contains an SIB byte). Non-indexed memory accesses lacked the
SIB byte check, which this patch adds.
2018-11-14 13:08:54 -08:00
Dan Gohman
f6617afcdd Remove the build time and directory from cranelift-codegen-meta's output.
This makes its output nondeterministic, making it friendier for
compilation caching tools.
2018-11-14 13:03:00 -08:00
oooooba
155fd4c72a Eliminate call stack recursion in VirtRegs::find (#584)
* Eliminate call stack recursion in VirtRegs::find
2018-11-14 12:58:50 -08:00
Dan Gohman
c2f5bc00a5 Fix typos in comments. 2018-11-12 15:15:02 -08:00
Dan Gohman
cd7c57e598 Make spilling visit fallthrough_return instructions too.
This is a followup to af2a952aabd82cf401cc664d0262b139ff92d86b. It
teaches the spilling pass to use the is_ghost() property to test whether
to visit instructions. This fixes a bug handling multiple return values
with fallthrough_return.
2018-11-12 19:43:55 +01:00
Dan Gohman
f3ea2d5d66 Tidy up documentation comment syntax. 2018-11-12 06:38:50 -08:00
Dan Gohman
076850549d Clarify an assertion error message. 2018-11-12 06:38:46 -08:00
Dan Gohman
7b27fdbf54 Avoid cloning an InstructionData when it isn't needed. 2018-11-09 15:13:42 -08:00
Dan Gohman
a0c2b40c17 Remove unnecessary pub keywords. 2018-11-09 15:11:03 -08:00
Dan Gohman
d54569cbdd Fix a typo in a comment. 2018-11-09 15:10:17 -08:00
Benjamin Bouvier
ce2364ddd9 [build] Remove dead code in Python and move assertions to the Rust code generator; 2018-11-09 09:23:36 -08:00
Benjamin Bouvier
add4043bb5 [build] Introduce a TargetIsaBuilder to better encapsulate the TargetIsa;
It was the caller's responsibility to call TargetIsa::check() before;
now one can't manipulate a TargetIsa without calling the
TargetIsaBuilder::finish() method, which is less error-prone and more in
line with what's coming for other things we're going to generate in the
meta crate.

Also splits the construction of a RegClass in two parts: a prototype is
made first when declaring the RegClass, and missing bits are filled in
when adding it to the TargetIsa(Builder). This avoids an awkward passing
of the isa to the RegClass ctor.
2018-11-09 09:23:36 -08:00
Benjamin Bouvier
f896bfb946 Prefix fixed_results/fixed_value_arguments with num to indicate they return a usize; 2018-11-08 11:41:04 -08:00
Dan Gohman
1d14f5ddbd Use cranelift-entity with default features.
The meta crate doesn't need to support no_std, so it can just use
default settings.
2018-11-07 16:24:19 -08:00
Dan Gohman
14dfc0d1b6 Bump version to 0.23.0. 2018-11-07 16:18:04 -08:00
Dan Gohman
38e8667f97 Adjust whitespace to match the upstream exception text.
This is a whitespace-only change.
2018-11-07 16:07:51 -08:00
Dan Gohman
fd875c3f5a Pass TargetFrontendConfig by value rather than by reference. 2018-11-07 16:01:15 -08:00
Dan Gohman
b476f823d4 Update to target_lexicon 0.2.0. 2018-11-07 16:01:15 -08:00
Lachlan Sneff
3409af7c07 Add early-stage optimization crate (#556)
* Add simple constant folding and folding tests
2018-11-07 15:59:29 -08:00
Dan Gohman
bdcc06eb15 When lowering br_table to branches, delete the old jump tables.
This prevents codegen from emitting unused readonly data.
2018-11-07 11:49:51 +01:00
Dan Gohman
997424a4c5 Add more comments explaining ghost instructions. 2018-11-07 11:03:23 +01:00
Dan Gohman
26da67b394 Add a verifier check that ghost instructions don't have encodings. 2018-11-07 11:03:23 +01:00
Dan Gohman
88bbbca6cd Make regalloc visit fallthrough_return instructions.
Add an explicit "is_ghost" property to selected instructions, and use
that to determine whether reload and coloring should visit instructions.
This allows them to visit fallthrough_return instructions and insert
fills and register moves as needed.
2018-11-07 11:03:23 +01:00
Dan Gohman
681cb5e20a Assert that the non-fixed inputs to return match the function's signature. 2018-11-07 10:51:19 +01:00
Dan Gohman
05c0b3bdd1 Insert copies to support a value being used as multiple return values.
When one value is used multiple times for separate return values, we
need to copy it to produce a new value, so that each value can be
allocated a different register.
2018-11-07 10:51:19 +01:00
Benjamin Bouvier
bcbb2d01cc [build] Stop using Python code to generate the register files; 2018-11-06 13:12:17 -08:00
Benjamin Bouvier
b7f2acf0ea [build] Implement registers code generation in the Rust meta crate; 2018-11-06 13:12:17 -08:00
Benjamin Bouvier
4f2d7dd54f [build] Move Isa enum to the meta library; 2018-11-06 13:12:17 -08:00
Benjamin Bouvier
17e88ed1c5 [build] Use the Rust-generated types files in place of the Python one; 2018-11-06 13:12:17 -08:00
Dan Gohman
a5cad9a748 Fix a typo in a comment. 2018-11-02 13:56:38 -07:00
Dan Gohman
d4f8eb7453 Introduce a TargetFrontendConfig type. (#570)
* Introduce a `TargetFrontendConfig` type.

`TargetFrontendConfig` is information specific to the target which is
provided to frontends to allow them to produce Cranelift IR for the
target. Currently this includes the pointer size and the default calling
convention.

The default calling convention is now inferred from the target, rather
than being a setting. cranelift-native is now just a provider of target
information, rather than also being a provider of settings, which gives
it a clearer role.

And instead of having cranelift-frontend routines require the whole
`TargetIsa`, just require the `TargetFrontendConfig`, and add a way to
get the `TargetFrontendConfig` from a `Module`.

Fixes #529.
Fixes #555.
2018-11-02 13:51:42 -07:00
Joe Howarth
7094d9f470 Prefix verifier errors with ; (#585)
* Prefix verifier errors with ;

extract arrow drawing code into helper
print ; at beginning of line followed by arrow and error body
2018-11-02 13:47:39 -07:00
Dan Gohman
9471c06da4 Update to use newer Rust features.
This re-introduces several cleanups that we previously deferred for not
supporting Rust 1.25.
2018-10-31 12:54:16 -07:00
Dan Gohman
0b769f5020 Use Display rather than having an explicit name() function for types.
This is more idiomatic Rust.
2018-10-30 11:45:35 +01:00
theJosher
d2b3ff6183 Errors reported by mypy 0.641 #558 2018-10-29 19:53:43 -07:00
Dan Gohman
f1db50aa76 Fix constant-offset folding to use the correct operand for stores. 2018-10-29 16:18:12 +01:00
Dan Gieschen Knutson
a19c6088f0 use iterative rather than recursive method for following aliases (#573)
* use iterative rather than recursive method for following aliases

* this avoids consuming stack via plain recursive calls
2018-10-28 20:26:44 -07:00
Dan Gohman
1b21d3a90e Fix the path to cdsl/types.py in a comment. 2018-10-26 11:22:43 -07:00
Dan Gohman
a2fcb32245 Escape backslashes in Python comments.
The latest version of flake8 diagnoses these as invalid escape
sequences, so properly escape them.
2018-10-24 10:00:42 -07:00
Boris-Chengbiao Zhou
b288c6001a Fix all clippy warnings (#564)
* Fix all clippy warnings

* Revert usage of inclusive ranges

* Remove redundant function argument

* Revert use of unavailable pointer methods

* Introduce ContiguousCaseRange
2018-10-22 21:52:35 -07:00
Lachlan Sneff
586a8835e9 Add a readonly flag for loads (#562)
* Add readonly MemFlag

* Add readonly flag verifier check

* Make global loads readonly

* Fix gvn to consider readonly loads
2018-10-22 21:50:09 -07:00
Benjamin Bouvier
3ec21459c5 Remove verify! macro that's used only once; 2018-10-19 16:10:05 -07:00
Dan Gohman
54ab1ea533 Optimize load/store with an iadd_imm operand.
Fold the immediate into the load/store offset when possible.
2018-10-19 10:58:55 -07:00
Benjamin Bouvier
9d6821d6d9 Fix #335: Introduce variable size recipes and remove GPR_SAFE reg classes (#552)
* Rename size to base_size and introduce a compute_size function;

* Add infra to inspect in/outs registers when computing the size of an instruction;

* Remove the GPR_SAFE_DEREF and GPR_ZERO_DEREF_SAFE register classes on x86 (fixes #335);
2018-10-15 15:43:38 -07:00