Use the new ISA predicate numbering to emit ISA predicate instructions in the
encoding tables.
Properly decode the ISA predicate number in RISC-V and add tests for RV32M iwth
and without 'supports_m' enabled.
Three predicates affect each extension:
- supports_m determines whether the target CPU supports the instruction set.
- enable_m determines if the instructions should be used, assuming they're
available.
- use_m is the predicate used to actually use the instructions.
Define data types for the level 1 and level 2 hash tables. These data types are
generic over the offset integer type so they can be twice as compact for
typically small ISAs.
Use these new types when generating encoding hash tables.
Emit both level 1 and level 2 hash tables.
Define generic functions that perform lookups in the encoding tables.
Implement the TargetIsa::encode() method for RISC-V using these building
blocks.
Add an isa::lookup() function which serves as a target registry for creating
Box<TargetIsa> trait objects.
An isa::Builder makes it possible to confugure the trait object before it is
created.
- Move detail data structures into a settings::detail module to avoid polluting
the settings namespace.
- Rename generated data types to 'Flags' in anticipation of computed predicate
flags that can't be set. The Flags struct is immutable.
- Use a settings::Builder struct to manipulate settings, then pass it to
Flags::new().
This trait allows settings to be manipulated as strings, using descriptors and
constant hash-table lookups.
Amend gen_settings.py to generate the necessary constant tables.
