Commit Graph

12 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
416b21c18d Pairwise virtual register coalescing.
Use a better algorithm for resolving interferences in virtual registers.
This improves code quality by generating much fewer copies on some
complicated functions.

After the initial union-find phase, the check_vreg() function uses a
Budimlic forest to check for interference between the values in the
virtual registers, as before. All the interference-free vregs are done.
Others are passed to synthesize_vreg() which dissolves the vreg and then
attempts to rebuild one or more vregs from the contained values.

The pairwise interference checks use *virtual copies* to make sure that
any future conflicts can be resolved by inserting a copy instruction.
This technique was not present in the old coalescer which caused some
correctness issues.

This coalescing algorithm makes much better code, and it is generally a
bit slower than before. Some of the slowdown is made up by the following
passes being faster because they have to process less code.

Example 1, the Python interpreter which contains a very large function
with a lot of variables.

Before:
  15.664    0.011  Register allocation
   1.535    1.535  RA liveness analysis
   2.872    1.911  RA coalescing CSSA
   4.436    4.436  RA spilling
   2.610    2.598  RA reloading
   4.200    4.199  RA coloring

After:
   9.795    0.013  Register allocation
   1.372    1.372  RA liveness analysis
   6.231    6.227  RA coalescing CSSA
   0.712    0.712  RA spilling
   0.598    0.598  RA reloading
   0.869    0.869  RA coloring

Coalescing is more than twice as slow, but because of the vastly better
code quality, overall register allocation time is improved by 37%.

Example 2, the clang compiler.

Before:
  57.148    0.035  Register allocation
   9.630    9.630  RA liveness analysis
   7.210    7.169  RA coalescing CSSA
   9.972    9.972  RA spilling
  11.602   11.572  RA reloading
  18.698   18.672  RA coloring

After:
  64.792    0.042  Register allocation
   8.630    8.630  RA liveness analysis
  22.937   22.928  RA coalescing CSSA
   8.684    8.684  RA spilling
   9.559    9.551  RA reloading
  14.939   14.936  RA coloring

Here coalescing is 3x slower, but overall regalloc time only regresses
by 13%.

Most examples are less extreme than these two. They just get better code
at about the same compile time.
2018-01-24 14:54:32 -08:00
Jakob Stoklund Olesen
d2e786a78a Resurrect the VirtRegs::unify() function.
The coalescer needs to be able to merge virtual registers with this
function.

Updated to recycle all virtual registers.
2018-01-23 14:21:36 -08:00
Jakob Stoklund Olesen
1e2b7de141 Remove dead code. 2018-01-16 12:34:32 -08:00
Jakob Stoklund Olesen
16ac4f65b3 Add support for textbook union-find to VirtRegs.
The initial phase of computing virtual registers can now be implemented
with a textbook union-find algorithm using a disjoint set forest
complete with rank and path compression optimizations.

The disjoint set forest is converted to virtual register value lists in
a single linear scan implemented in finish_union_find().

This union-find algorithm will soon be used by the coalescer.
2018-01-16 12:32:04 -08:00
Jakob Stoklund Olesen
2473661d49 Loosen the required order of values in a virtual register.
Instead of requiring the values in a virtual register to be sorted
according to the domtree.rpo_cmp() order, just require any topological
ordering w.r.t. dominance.

The coalescer with stop using the RPO shortly.
2017-12-13 15:25:21 -06:00
Jakob Stoklund Olesen
2e0b931590 Provide an fmt::Debug impl for entity references.
Instead of deriving a Debug impl: Ebb(45), use the Display version for
Debug too: ebb45.

This is more readable, and no information is lost.
2017-11-21 10:01:55 -08:00
Dan Gohman
3ab4349c1b Use Self instead of repeating the type name. 2017-11-08 10:43:11 -08:00
Dan Gohman
2efdc0ed37 Update rustfmt to 0.9.0. 2017-08-31 10:44:59 -07:00
Jakob Stoklund Olesen
9cb0529be4 Move EntityList and SparseMap into the entity module.
These data structures are dependent on EntityRef and EntityMap, so it
makes sense to keep them in the same module.
2017-08-18 16:14:06 -07:00
Jakob Stoklund Olesen
7e08b14cf6 Split EntityMap into entity::PrimaryMap and entity::EntityMap.
The new PrimaryMap replaces the primary EntityMap and the PrimaryEntityData
marker trait which was causing some confusion. We now have a clear
division between the two types of maps:

- PrimaryMap is used to assign entity numbers to the primary data for an
  entity.
- EntityMap is a secondary mapping adding additional info.

The split also means that the secondary EntityMap can now behave as if
all keys have a default value. This means that we can get rid of the
annoying ensure() and get_or_default() methods ther were used everywhere
instead of indexing. Just use normal indexing now; non-existent keys
will return the default value.
2017-08-18 16:04:43 -07:00
Jakob Stoklund Olesen
6d6035b918 CSSA verifier.
During register allocation, the code must be kept in conventional SSA
form. Add a verifier that checks this property.
2017-07-13 13:18:18 -07:00
Jakob Stoklund Olesen
d5055275c4 Virtual registers.
Add a VirtRegs collection which tracks virtual registers.

A virtual register is a set of related SSA values whose live ranges
don't interfere. It is advantageous to use the same register or spill
slot for al the values in a virtual register. It reduces copies for EBB
arguments.
2017-06-22 14:51:10 -07:00