Move EntityList and SparseMap into the entity module.

These data structures are dependent on EntityRef and EntityMap, so it
makes sense to keep them in the same module.

lib/cretonne/src/entity/mod.rs

@@ -6,12 +6,16 @@
 //! Various data structures based on the entity references are defined in sub-modules.
 
 mod keys;
+mod list;
 mod map;
 mod primary;
+mod sparse;
 
 pub use self::keys::Keys;
+pub use self::list::{EntityList, ListPool};
 pub use self::map::EntityMap;
 pub use self::primary::PrimaryMap;
+pub use self::sparse::{SparseSet, SparseMap, SparseMapValue};
 
 /// A type wrapping a small integer index should implement `EntityRef` so it can be used as the key
 /// of an `EntityMap` or `SparseMap`.

lib/cretonne/src/ir/instructions.rs

@@ -17,17 +17,17 @@ use ir::condcodes::*;
 use ir::types;
 use isa::RegUnit;
 
-use entity_list;
+use entity;
 use bitset::BitSet;
 use ref_slice::{ref_slice, ref_slice_mut};
 
 /// Some instructions use an external list of argument values because there is not enough space in
 /// the 16-byte `InstructionData` struct. These value lists are stored in a memory pool in
 /// `dfg.value_lists`.
-pub type ValueList = entity_list::EntityList<Value>;
+pub type ValueList = entity::EntityList<Value>;
 
 /// Memory pool for holding value lists. See `ValueList`.
-pub type ValueListPool = entity_list::ListPool<Value>;
+pub type ValueListPool = entity::ListPool<Value>;
 
 // Include code generated by `lib/cretonne/meta/gen_instr.py`. This file contains:
 //

lib/cretonne/src/lib.rs

@@ -18,7 +18,6 @@ pub mod entity;
 pub mod binemit;
 pub mod bitset;
 pub mod dominator_tree;
-pub mod entity_list;
 pub mod flowgraph;
 pub mod ir;
 pub mod isa;
@@ -27,7 +26,6 @@ pub mod packed_option;
 pub mod regalloc;
 pub mod result;
 pub mod settings;
-pub mod sparse_map;
 pub mod verifier;
 
 mod abi;

lib/cretonne/src/licm.rs

@@ -4,7 +4,7 @@ use ir::{Function, Ebb, Inst, Value, Cursor, CursorBase, Type, InstBuilder, Layo
 use flowgraph::ControlFlowGraph;
 use std::collections::HashSet;
 use dominator_tree::DominatorTree;
-use entity_list::{EntityList, ListPool};
+use entity::{EntityList, ListPool};
 use loop_analysis::{Loop, LoopAnalysis};
 
 /// Performs the LICM pass by detecting loops within the CFG and moving

lib/cretonne/src/regalloc/live_value_tracker.rs

@@ -5,7 +5,7 @@
 //! instruction, starting at the EBB header.
 
 use dominator_tree::DominatorTree;
-use entity_list::{EntityList, ListPool};
+use entity::{EntityList, ListPool};
 use ir::instructions::BranchInfo;
 use ir::{Inst, Ebb, Value, DataFlowGraph, Layout, ExpandedProgramPoint};
 use partition_slice::partition_slice;

lib/cretonne/src/regalloc/liveness.rs

@@ -175,13 +175,13 @@
 //!
 //! There is some room for improvement.
 
+use entity::SparseMap;
 use flowgraph::ControlFlowGraph;
 use ir::dfg::ValueDef;
 use ir::{Function, Value, Inst, Ebb, Layout, ProgramPoint};
 use isa::{TargetIsa, EncInfo};
 use regalloc::affinity::Affinity;
 use regalloc::liverange::LiveRange;
-use sparse_map::SparseMap;
 use std::mem;
 use std::ops::Index;
 

lib/cretonne/src/regalloc/liverange.rs

@@ -107,10 +107,10 @@
 //! of coalescing, so we would need to roll our own.
 //!
 
-use std::cmp::Ordering;
+use entity::SparseMapValue;
 use ir::{Inst, Ebb, Value, ProgramPoint, ExpandedProgramPoint, ProgramOrder};
 use regalloc::affinity::Affinity;
-use sparse_map::SparseMapValue;
+use std::cmp::Ordering;
 
 /// Global live range of a single SSA value.
 ///

lib/cretonne/src/regalloc/reload.rs

@@ -11,6 +11,7 @@
 
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
+use entity::{SparseMap, SparseMapValue};
 use ir::{Ebb, Inst, Value, Function};
 use ir::{InstBuilder, ArgumentType, ArgumentLoc};
 use isa::RegClass;
@@ -18,7 +19,6 @@ use isa::{TargetIsa, Encoding, EncInfo, RecipeConstraints, ConstraintKind};
 use regalloc::affinity::Affinity;
 use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use regalloc::liveness::Liveness;
-use sparse_map::{SparseMap, SparseMapValue};
 use topo_order::TopoOrder;
 
 /// Reusable data structures for the reload pass.

lib/cretonne/src/regalloc/solver.rs

@@ -105,10 +105,10 @@
 //! appropriate candidate among the set of live register values, add it as a variable and start
 //! over.
 
+use entity::{SparseMap, SparseMapValue};
 use ir::Value;
 use isa::{RegInfo, RegClass, RegUnit};
 use regalloc::allocatable_set::RegSetIter;
-use sparse_map::{SparseMap, SparseMapValue};
 use std::fmt;
 use super::AllocatableSet;
 

lib/cretonne/src/regalloc/virtregs.rs

@@ -11,7 +11,7 @@
 //! If any values in a virtual register are spilled, they will use the same stack slot. This avoids
 //! memory-to-memory copies when a spilled value is passed as an EBB argument.
 
-use entity_list::{EntityList, ListPool};
+use entity::{EntityList, ListPool};
 use entity::{PrimaryMap, EntityMap, Keys};
 use ir::Value;
 use packed_option::PackedOption;

lib/cretonne/src/topo_order.rs

@@ -1,8 +1,8 @@
 //! Topological order of EBBs, according to the dominator tree.
 
+use entity::SparseSet;
 use dominator_tree::DominatorTree;
 use ir::{Ebb, Layout};
-use sparse_map::SparseSet;
 
 /// Present EBBs in a topological order such that all dominating EBBs are guaranteed to be visited
 /// before the current EBB.

lib/cretonne/src/verifier/mod.rs

@@ -58,6 +58,7 @@
 
 use dbg::DisplayList;
 use dominator_tree::DominatorTree;
+use entity::SparseSet;
 use flowgraph::ControlFlowGraph;
 use ir;
 use ir::entities::AnyEntity;
@@ -65,7 +66,6 @@ use ir::instructions::{InstructionFormat, BranchInfo, ResolvedConstraint, CallIn
 use ir::{types, Function, ValueDef, Ebb, Inst, SigRef, FuncRef, ValueList, JumpTable, StackSlot,
          StackSlotKind, GlobalVar, Value, Type, Opcode, ValueLoc, ArgumentLoc};
 use isa::TargetIsa;
-use sparse_map::SparseSet;
 use std::error as std_error;
 use std::fmt::{self, Display, Formatter};
 use std::result;