Commit Graph

2945 Commits

Author SHA1 Message Date
Benjamin Bouvier
f721821bec [contribution] Add Github issue templates; 2019-10-22 15:33:09 +02:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats;
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
9e9a7626d7 [meta] Use a ref-counted pointer to an InstructionFormat in instructions;
This avoids a lot of dereferences, and InstructionFormat are immutable
once they're created. It removes a lot of code that was keeping the
FormatRegistry around, just in case we needed the format. This is more
in line with the way we create Instructions, and make it easy to
reference InstructionFormats in general.
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
8fece43aa1 [meta] Use a type alias for Instruction;
... instead of embedding a Rc<InstructionContent>, just make it a type
alias.
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d102bf9b61 Add allow(dead_code) for Immediate until it's used in legalization patterns; (#1157) 2019-10-18 08:05:01 -06:00
Andrew Brown
135f9eb4a6 Translate WASM bitselect to CLIF 2019-10-17 15:49:29 -07:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
8f74333662 Add x86 SIMD band_not 2019-10-17 15:49:29 -07:00
Sean Stangl
fad6bb1a5c Fix build by marking tests as incompatible with basic-blocks. Closes #1152 2019-10-17 12:00:22 -07:00
Sean Stangl
46b44ad82d Increase legibility of the SSABuilder (#1142) 2019-10-17 11:30:38 -06:00
Benjamin Bouvier
a3f55cdf1f Regalloc solver: check that a variable doesn't exist to test if it can be added (fixes #1123);
This situation could be triggered that can_add_var would return true
while a variable was already added for the given register.

For instance, when we have a reassignment (because of a fixed register
input requirement) and a fixed input conflict on the same fixed
register, this register will not be available in the regs_in set after
inputs_done (because of the fixed input conflict diversion) but will
have its own variable.
2019-10-17 08:42:08 -07:00
Benjamin Bouvier
beca77c2f8 Regalloc: rename "constraint" to "rc" and "op" to "constraint"; 2019-10-17 08:42:08 -07:00
dependabot-preview[bot]
05cc8823c2 Update raw-cpuid requirement from 6.0.0 to 7.0.3
Updates the requirements on [raw-cpuid](https://github.com/gz/rust-cpuid) to permit the latest version.
- [Release notes](https://github.com/gz/rust-cpuid/releases)
- [Commits](https://github.com/gz/rust-cpuid/compare/6.0...7.0.3)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
2019-10-17 17:15:21 +02:00
Nicolas B. Pierron
69d2f40c10 Fix #796: Enable basic-blocks by default. 2019-10-17 14:00:40 +02:00
Nicolas B. Pierron
7c31ce40c4 i128-isplit-forward-jump.clif: BB conditional branches can only be followed by a jump statement. 2019-10-17 13:59:04 +02:00
dependabot-preview[bot]
e15b720d56 Update indicatif requirement from 0.11.0 to 0.12.0
Updates the requirements on [indicatif](https://github.com/mitsuhiko/indicatif) to permit the latest version.
- [Release notes](https://github.com/mitsuhiko/indicatif/releases)
- [Commits](https://github.com/mitsuhiko/indicatif/compare/0.11.0...0.12.0)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
2019-10-16 12:29:14 +02:00
Andrew Brown
19a980363e Translate WASM shr to CLIF sshr and ushr
As with shift left, the spec requires that the shift count is computed modulo the lane width (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#left-shift-by-scalar).
2019-10-15 15:51:50 -07:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
2019-10-15 15:51:50 -07:00
Andrew Brown
808885ce56 Translate WASM shl to CLIF ishl
Note how, according to the spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#left-shift-by-scalar), the shift count is computed modulo the lane width. E.g., a shift count of 17 on an i16x8 should not result in all zeroes as it does with Cranelift's `ishl` and x86's `PSSLW`--it should shift once to the left.
2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
2019-10-15 15:51:50 -07:00
Andrew Brown
67733bd2fc Use ConstantData exclusively for inserting data into the constant pool
Previously we allowed anything that could be converted into ConstantData (e.g. a Vec).
2019-10-15 15:19:00 -07:00
Andrew Brown
a69b0fc221 Change match_literals_to_uimm128 to match_literals_to_constant_data 2019-10-15 15:19:00 -07:00
Andrew Brown
ff93564c55 Update predicate documentation to match new ConstantData parameter 2019-10-15 15:19:00 -07:00
Andrew Brown
a03f905d08 Replace V128Imm functionality with ConstantData
This moves most original uses of V128Imm (e.g. in parsing) to ConstantData and shifts the unit tests from V128Imm to ConstantData.
2019-10-15 15:19:00 -07:00
Andrew Brown
1600dba634 Make ConstantData a container for any-size constant values
Previously, ConstantData was a type alias for `Vec<u8>` which prevented it from having an implementation; this meant that `V128Imm` and `&[u8; 16]` were used in places that otherwise could have accepted types of different byte lengths.
2019-10-15 15:19:00 -07:00
Dan Gohman
50b7d2827d Bump version to 0.46.1 2019-10-15 11:11:48 -07:00
Nick Fitzgerald
bae0257fc3 cranelift-wasm: Fix reachability tracking for if .. else .. end
We weren't previously keeping track of quite the right information for whether
an `if .. else .. end`'s following block was reachable or not. It should be
reachable if the head is reachable and either the consequent or alternative end
reachable (and therefore fall through to the following block) or do an early
`br_if` to it.

This commit rejiggers `ControlStackFrame::If` to keep track of reachability at
the end of the consequent (we don't need to keep track of it at the end of the
alternative, since that is simply `state.reachable`) and adds Wasm tests for
every reachability situation we can encounter with `if .. else .. end`.

Fixes #1132
2019-10-15 10:37:59 -07:00
Dan Gohman
ac4e93f971 Bump version to 0.46.0 2019-10-15 09:43:28 -07:00
Benjamin Bouvier
5b274ed3ba [bugpoint] Merge consecutive blocks (fixes #1124); 2019-10-15 14:34:58 +02:00
Benjamin Bouvier
ab42f322d4 [bugpoint] Don't test for a crash when a mutation doesn't change anything; 2019-10-15 14:34:58 +02:00
Benjamin Bouvier
735d4c7aef [bugpoint] Make the mutation_count non optional; 2019-10-15 14:34:58 +02:00
Benjamin Bouvier
012fca61f9 [bugpoint] Use a unique progress bar and simplify Mutator trait; 2019-10-15 14:34:58 +02:00
Benjamin Bouvier
6b7304cb14 [bugpoint] Implement replacing a single instruction by several ones;
This allows replacing a function that has N results with N instructions
with the same result type. It also narrows down typing, so that
instructions creating F32/F64 values are replaced with a constant of the
correct type.
2019-10-15 14:34:58 +02:00
Benjamin Bouvier
0340ddbb65 [bugpoint] Move test content to the tests/ directory; 2019-10-15 14:34:58 +02:00
Benjamin Bouvier
a5efd2a625 [bugpoint] Cosmetic improvements;
- Mostly Rust improvements to make code look more idiomatic.
- Also reuses the code memory accross compilation, to avoid many
memory allocations.
2019-10-15 14:34:58 +02:00
Benjamin Bouvier
48ccb3e051 [ci] Disable cargo fuzz on macos nightly;
It has started breaking in ways unrelated to Cranelift, making it hard
to spot real CI failures in Cranelift. We should re-enable it at some
point, but disable it in the meanwhile.
2019-10-15 14:33:50 +02:00
Benjamin Bouvier
1ccf056baf [wasm] Make the ModuleTranslationState ctor public.
It's useful for consumers which don't want to translate a whole module,
but just need translation of functions.
2019-10-15 13:58:56 +02:00
Benjamin Bouvier
566a143634 [meta] Add pub(crate) to more types;
This caught one unused method, allowing us to remove it.
2019-10-15 11:37:48 +02:00
Benjamin Bouvier
d3ef80147b [meta] Simplify handling of variable arguments in legalization;
If a legalization contains varargs, it defers creating the binding for
the varargs, making the generated code easier to understand.
2019-10-15 11:37:48 +02:00
Benjamin Bouvier
687604d33a [meta] Legalization: don't emit a spurious if true for transforms that always apply;
This enhances readability of the generated legalizer code by replacing
`if true { body }` with `body`.
2019-10-15 11:37:48 +02:00
Benjamin Bouvier
350b3b2406 [meta] Avoid unwrapping instructions several times during legalization;
This avoids doing multiple unpacking of the InstructionData for a single
legalization, improving readability and reducing size of the generated
code. For instance, icmp had to unpack the format once per IntCC
condition code.
2019-10-15 11:37:48 +02:00
Nick Fitzgerald
ca53090f1b cranelift-wasm: Create ModuleTranslationState and polish API a little (#1111)
* cranelift-wasm: replace `WasmTypesMap` with `ModuleTranslationState`

The `ModuleTranslationState` contains information decoded from the Wasm module
that must be referenced during each Wasm function's translation.

This is only for data that is maintained by `cranelift-wasm` itself, as opposed
to being maintained by the embedder. Data that is maintained by the embedder is
represented with `ModuleEnvironment`.

A `ModuleTranslationState` is returned by `translate_module`, and can then be
used when translating functions from that module.

* cranelift-wasm: rename `TranslationState` to `FuncTranslationState`

To disambiguate a bit with the new `ModuleTranslationState`.

* cranelift-wasm: Reorganize the internal `state` module into submodules

One module for the `ModuleTranslationState` and another for the
`FuncTranslationState`.

* cranelift-wasm: replace `FuncTranslator` with methods on `ModuleTranslationState`

`FuncTranslator` was two methods that always took ownership of `self`, so it
didn't really make sense as an object as opposed to two different functions, or
in this case methods on the object that actually persists for a longer time.

I think this improves ergonomics nicely.

Before:

```rust
let module_translation = translate_module(...)?;
for body in func_bodies {
    let mut translator = FuncTranslator::new();
    translator.translate(body, ...)?;
}
```

After:

```rust
let module_translation = translate_module(...)?;
for body in func_bodies {
    module_translation.translate_func(body, ...)?;
}
```

Note that this commit does not remove `FuncTranslator`. It still exists, but is
just a wrapper over the `ModuleTranslationState` methods, and it is marked
deprecated, so that downstream users get a heads up. This should make the
transition easier.

* Revert "cranelift-wasm: replace `FuncTranslator` with methods on `ModuleTranslationState`"

This reverts commit 075f9ae933bcaae39348b61287c8f78a4009340d.
2019-10-11 12:37:17 -07:00
Andrew Brown
b19f804ed5 Convert WASM logical operators to CLIF 2019-10-11 11:05:24 -07:00
Andrew Brown
1f728c1797 Add x86 legalization for SIMD bnot 2019-10-11 11:05:24 -07:00
Andrew Brown
4c56516d3f Allow creating constants in legalization AST
This adds a `DummyConstant` structure that is converted to something like `let const0 = pos.func.dfg.constants.insert(...)` in `gen_legalizer.rs`. This allows us to create constants during legalization with something like `let ones = constant(vec![0xff; 16])` and then use `ones` within a `def!` block, e.g.: `def!(a = vconst(ones))`. One unfortunate side-effect of this change is that, because the names of the constants in `ConstPool` are dynamic, the `VarPool` and `SymbolTable` structures that previously operated on `&'static str` types now must operate on `String` types; however, since this is a change to the meta code-generation, it should result in no runtime performance impact.
2019-10-11 11:05:24 -07:00
Andrew Brown
dbe7dd59da Add x86 SIMD bxor 2019-10-11 11:05:24 -07:00
Andrew Brown
4cdc1e76a4 Add x86 SIMD band 2019-10-11 11:05:24 -07:00
Andrew Brown
96d51cb1e8 Switch x86 SIMD bor from ORPS to POR encoding
There are two reasons for this change:
 1. it reduces confusion; using the `POR` encoding will match the future encodings of `band` and `bxor` and the `ORPS` encoding may be confusing as it is intended for floating-point operations
 2. `POR` has slightly more throughput: it only has to wait 0.33 cycles to execute again on all Intel architectures above Core whereas `ORPS` must wait 1 cycle on architectures older than Skylake (Intel Optimization Reference Manual, C.3)

`POR` does add one additional byte to the encoding and requires SSE2 so the `ORPS` opcode is left in for future use.
2019-10-11 11:05:24 -07:00
Benjamin Bouvier
5e87996275 [wasm] Make the WasmTypeMap constructor public; (#1125) 2019-10-10 12:19:53 -07:00