See long block comment in codegen.rs. In brief, I think we actually want
to compile to a trie with priority-intervals, a sort of hybrid of a
priority tree and a trie representing decisions keyed on match-ops
(PatternInsts).
The reasons are:
1. The lexicographic ordering that is fundamental to the FSM-building in
the Peepmatic view of the problem is sort of fundamentally limited
w.r.t. our notion of rule priorities. See the example in the block
comment.
2. While the FSM is nice for interpreter-based execution, when compiling
to a language with structured control flow, what we really want is a
tree; otherwise, if we want to form DAGs to share substructure, we
need something like a "diamond-recovery" algorithm that finds common
suffixes of *input match-op sequences*, and then we need to
incorporate something like phi-nodes in order to allow captures from
either side of the diamond to be used.
3. One of the main advantages of the automaton/transducer approach,
namely sharing suffixes of the *output* sequence (emitting partial
output at each state transition), is unfortunately not applicable if
we allow the overall function to be partial. Otherwise, there is
always the possibility that we fail at the last match op, so we
cannot allow any external constructors to be called until we reach
the final state anyway.
4. Pragmatically, I found I was having to significantly edit the
peepmatic_automata implementation to adapt to this use-case
(compilation to Rust), and it seemed more practical to design the
data structure we want than to try to shoehorn the existing thing
into the new problem.
WIP, hopefully working soon.
* Add some debug logging for timing in module compiles
This is sometimes helpful when debugging slow compiles from fuzz bugs or
similar.
* Fix total duration calculation to not double-count
Some platforms such as AArch64 Linux support different memory page
sizes, so we need to be conservative when choosing the code section
alignment (which is equal to the page size) by using the maximum.
Copyright (c) 2021, Arm Limited.
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate.
Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
* Fix some nightly dead code warnings
Looks like the "struct field not used" lint has improved on nightly and
caught a few more instances of fields that were never actually read.
* Fix windows
