Commit Graph

130 Commits

Author SHA1 Message Date
Darin Morrison
d68437e1e6 Update SIMD tests to use hex literals 2020-03-02 08:28:59 -08:00
bjorn3
0a1bb3ba6c Add TLS support for ELF and MachO (#1174)
* Add TLS support
* Add binemit and legalize tests
* Spill all caller-saved registers when necessary
2020-02-25 17:50:04 -08:00
Andrew Brown
032e81fd6f Add x86 SIMD average rounding 2020-02-24 09:48:38 -08:00
Andrew Brown
1a9dc743d1 Infer REX prefix for SIMD load instruction 2020-02-19 09:24:05 -08:00
Andrew Brown
936120dcf9 Infer REX prefix for SIMD store and vconst instructions 2020-02-19 09:24:05 -08:00
Peter Delevoryas
18b40d1101 Add ineg legalization for scalar integer types (#1385) 2020-02-14 13:16:02 -08:00
Ryan Hunt
832666c45e Mass rename Ebb and relatives to Block (#1365)
* Manually rename BasicBlock to BlockPredecessor

BasicBlock is a pair of (Ebb, Inst) that is used to represent the
basic block subcomponent of an Ebb that is a predecessor to an Ebb.

Eventually we will be able to remove this struct, but for now it
makes sense to give it a non-conflicting name so that we can start
to transition Ebb to represent a basic block.

I have not updated any comments that refer to BasicBlock, as
eventually we will remove BlockPredecessor and replace with Block,
which is a basic block, so the comments will become correct.

* Manually rename SSABuilder block types to avoid conflict

SSABuilder has its own Block and BlockData types. These along with
associated identifier will cause conflicts in a later commit, so
they are renamed to be more verbose here.

* Automatically rename 'Ebb' to 'Block' in *.rs

* Automatically rename 'EBB' to 'block' in *.rs

* Automatically rename 'ebb' to 'block' in *.rs

* Automatically rename 'extended basic block' to 'basic block' in *.rs

* Automatically rename 'an basic block' to 'a basic block' in *.rs

* Manually update comment for `Block`

`Block`'s wikipedia article required an update.

* Automatically rename 'an `Block`' to 'a `Block`' in *.rs

* Automatically rename 'extended_basic_block' to 'basic_block' in *.rs

* Automatically rename 'ebb' to 'block' in *.clif

* Manually rename clif constant that contains 'ebb' as substring to avoid conflict

* Automatically rename filecheck uses of 'EBB' to 'BB'

'regex: EBB' -> 'regex: BB'
'$EBB' -> '$BB'

* Automatically rename 'EBB' 'Ebb' to 'block' in *.clif

* Automatically rename 'an block' to 'a block' in *.clif

* Fix broken testcase when function name length increases

Test function names are limited to 16 characters. This causes
the new longer name to be truncated and fail a filecheck test. An
outdated comment was also fixed.
2020-02-07 10:46:47 -06:00
Ryan Hunt
c360007b19 Drop 'basic-blocks' feature (#1363)
* All: Drop 'basic-blocks' feature

This makes it so that 'basic-blocks' cannot be disabled and we can
start assuming it everywhere.

* Tests: Replace non-bb filetests with bb version

* Tests: Adapt solver-fixedconflict filetests to use basic blocks
2020-01-23 22:36:06 -07:00
jmkrauz
ae6ba1e58c Fix narrow_icmp_imm (#1343) 2020-01-21 15:20:44 +01:00
Benjamin Bouvier
dd497c19e1 Renames Settings ⚠️ (fixes #976) (#1321)
This is a breaking API change: the following settings have been renamed:

- jump_tables_enabled -> enable_jump_tables
- colocated_libcalls -> use_colocated_libcalls
- probestack_enabled -> enable_probestack
- allones_funcaddrs -> emit_all_ones_funcaddrs
2020-01-13 14:42:49 -07:00
Yury Delendik
bd88155483 Refactor unwind; add FDE support. (#1320)
* Refactor unwind

* add FDE support

* use sink directly in emit functions

* pref off all unwinding generation with feature
2020-01-13 10:32:55 -06:00
Andrew Brown
6fe86bcb61 Fix SIMD float comparison encoding (#1285)
The Intel manual uses `CMPNLT` and `CMPNLE` to denote not-less-than and not-less-than-or-equals. These were translated previously to `FloatCC::GreaterThan` and `FloatCC::GreaterThanOrEqual` but should be correctly translated to `FloatCC::UnorderedOrGreaterThanOrEqual` and `FloatCC::UnorderedOrGreaterThan`. This change adds the necessary legalizations to make use of these new encodings.
2020-01-08 09:28:05 -08:00
bjorn3
9bbe378d41 Fix master tests (#1316)
Co-authored-by: Benjamin Bouvier <public@benj.me>
2020-01-06 14:39:04 +01:00
Sean Stangl
cf9e762f16 Add a DynRex recipe type for x86, decreasing the number of recipes (#1298)
This patch adds a third mode for templates: REX inference is requestable
at template instantiation time. This reduces the number of recipes
by removing rex()/nonrex() redundancy for many instructions.
2019-12-19 15:49:34 -07:00
Andrew Brown
4433ad2858 Fix legalization of icmp ugt (#1278)
Previously, the same pattern (pmax + pcmpeq) as `uge` was used but this logic was incorrect for operands with equal values.
2019-12-16 14:14:51 -07:00
Andrew Brown
6181f20326 Fix legalization of SIMD fneg (#1286)
Previously `fsub` was used but this fails when negating -0.0 and +0.0 in the SIMD spec tests; using more instructions, this change uses shifts to create a constant for flipping the most significant bit of each lane with `bxor`.
2019-12-16 10:32:08 -08:00
Andrew Brown
0604ec480c Fix scalar_to_vector: move not wide enough for 64-bit values (#1287)
Previously, the use of `enc_x86_64` emitted two 64-bit mode encodings for `scalar_to_vector.i64`, neither of which contained the REX.W bit telling `MOVD/MOVQ` to move 64 bits of data instead of 32 bits. Now, `scalar_to_vector.i64` will always use a sole 64-bit mode REX.W encoding and `scalar_to_vector` with other widths will have three encodings: a 32-bit mode move, a 64-bit mode move with no REX, and a 64-bit mode move with REX (but not REX.W).
2019-12-16 10:17:08 -08:00
bjorn3
4cc0241f37 More i8 legalizations (#1253)
* Legalize stack_{load,store}.i8, fixes #433
* Legalize select.i8, cc: #466
* Legalize brz.i8 and brnz.i8, cc: #1117
2019-12-04 09:16:22 -08:00
krk
bc9f05e5e2 Add legalization for bitrev.i128 via narrowing, fixes #1116 (#1229) 2019-11-22 12:38:04 +01:00
bjorn3
c5e74986e1 Legalize uextend and sextend to 128bit ints 2019-11-19 14:42:21 -08:00
Andrew Brown
91d29c09d0 Add x86 SIMD floating-point absolute value 2019-11-15 13:45:25 -08:00
Andrew Brown
1f17e35e95 Add x86 SIMD immediate shifts 2019-11-15 13:45:25 -08:00
Andrew Brown
6519a43b08 Add x86 SIMD floating-point negation 2019-11-15 13:45:25 -08:00
Andrew Brown
c8eb4e9612 Add x86 SIMD floating-point arithmetic 2019-11-12 17:05:39 -08:00
Andrew Brown
04db2a9f39 Bind constant vectors to vconst; fixes #1052 (#1217) 2019-11-12 15:57:59 -08:00
Benjamin Bouvier
9080a02e10 Replace CraneStation by bytecodealliance everywhere; (#1221) 2019-11-12 10:09:31 -08:00
Andrew Brown
d32301854d Add x86 SIMD implementation of float comparison 2019-11-08 14:06:53 -08:00
Benjamin Bouvier
143cb01489 Do not align the stack frame for leaf functions not using the stack. 2019-11-08 17:20:20 +01:00
Andrew Brown
af4637aff6 Add x86 SIMD legalizations for icmp less-than 2019-11-05 16:42:34 -08:00
Andrew Brown
feffed85d2 Add x86 SIMD legalizations for integer greater-than
This includes `icmp ugt`, `icmp sge`, and `icmp uge` for vectors with lanes of I8, I16, and I32.
2019-11-05 16:42:34 -08:00
Andrew Brown
0ab5760fd7 Add x86 SIMD instructions for min and max
Only the I8, I16, and I32 versions are included since Cranelift lacks support for AVX.
2019-11-05 16:42:34 -08:00
Andrew Brown
c454c3c771 Add x86 SIMD encoding for icmp sgt 2019-11-05 16:42:34 -08:00
Andrew Brown
e3a20d67b2 Add x86 SIMD legalization of icmp ne 2019-11-05 16:42:34 -08:00
Peter Huene
8923bac7e8 Implement emitting Windows unwind information for fastcall functions. (#1155)
* Implement emitting Windows unwind information for fastcall functions.

This commit implements emitting Windows unwind information for x64 fastcall
calling convention functions.

The unwind information can be used to construct a Windows function table at
runtime for JIT'd code, enabling stack walking and unwinding by the operating
system.

* Address code review feedback.

This commit addresses code review feedback:

* Remove unnecessary unsafe code.
* Emit the unwind information always as little endian.
* Fix comments.

A dependency from cranelift-codegen to the byteorder crate was added.
The byteorder crate is a no-dependencies crate with a reasonable
abstraction for writing binary data for a specific endianness.

* Address code review feedback.

* Disable default features for the `byteorder` crate.
* Add a comment regarding the Windows ABI unwind code numerical values.
* Panic if we encounter a Windows function with a prologue greater than 256
  bytes in size.
2019-11-05 13:14:30 -08:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
2019-10-22 11:01:05 -07:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
8f74333662 Add x86 SIMD band_not 2019-10-17 15:49:29 -07:00
Nicolas B. Pierron
7c31ce40c4 i128-isplit-forward-jump.clif: BB conditional branches can only be followed by a jump statement. 2019-10-17 13:59:04 +02:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
2019-10-15 15:51:50 -07:00
Andrew Brown
1f728c1797 Add x86 legalization for SIMD bnot 2019-10-11 11:05:24 -07:00
Andrew Brown
dbe7dd59da Add x86 SIMD bxor 2019-10-11 11:05:24 -07:00
Andrew Brown
4cdc1e76a4 Add x86 SIMD band 2019-10-11 11:05:24 -07:00
Ujjwal Sharma
f1c25c2c5a [codegen] legalize imul for 64-bit and 128-bit operands
Add a legalization that legalizes imul.I64 for 32-bit ISAs and imul.I128
for 64-bit (and subsequently 32-bit) ISAs.

Refs: https://github.com/bnjbvr/cranelift-x86/issues/4
2019-10-10 17:39:40 +02:00
Ujjwal Sharma
c062f12d7c [codegen] legalize icmp for 64 and 128 bit operands
Add legalizations for icmp and icmp_imm for i64 and i128 operands for
the narrow legalization set, allowing 32-bit ISAs (like x86-32) to
compare 64-bit integers and all ISAs to compare 128-bit integers.

Fixes: https://github.com/bnjbvr/cranelift-x86/issues/2
2019-10-10 11:06:19 +02:00
bjorn3
68b671e0ee Fix isplit legalization for ebb params when jumping forward
Fixes #1106
2019-10-09 08:56:48 -07:00
Benjamin Bouvier
a9d9f9f135 Write a run test for brz.i128; 2019-10-02 13:43:44 +02:00
bjorn3
093b3b3426 Fix brz.i128
Fixes #1066
2019-10-02 11:04:29 +02:00
Andrew Brown
d8967bb58a Split SIMD arithmetic tests by test directive 2019-09-30 13:54:30 -07:00