Implement UwidenLow and UwidenHigh for the interpreter
Implemented `UwidenLow` and `UwidenHigh` for the Cranelift interpreter, doubling the width and halving the number of lanes preserving the low and high halves respectively. Conversions are performed using unsigned zero extension. Copyright (c) 2021, Arm Limited
This commit is contained in:
26
cranelift/filetests/filetests/runtests/simd-uwidenhigh.clif
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26
cranelift/filetests/filetests/runtests/simd-uwidenhigh.clif
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@@ -0,0 +1,26 @@
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test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64
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function %uwidenhigh_i8x16(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = uwiden_high v0
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return v1
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}
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; run: %uwidenhigh_i8x16([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]) == [9 10 11 12 13 14 15 16]
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function %uwidenhigh_i16x8(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = uwiden_high v0
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return v1
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}
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; run: %uwidenhigh_i16x8([1 2 3 4 5 6 7 8]) == [5 6 7 8]
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function %uwidenhigh_i32x4(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = uwiden_high v0
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return v1
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}
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; run: %uwidenhigh_i32x4([1 2 3 4]) == [3 4]
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26
cranelift/filetests/filetests/runtests/simd-uwidenlow.clif
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cranelift/filetests/filetests/runtests/simd-uwidenlow.clif
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@@ -0,0 +1,26 @@
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test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64
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function %uwidenlow_i8x16(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = uwiden_low v0
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return v1
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}
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; run: %uwidenlow_i8x16([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]) == [1 2 3 4 5 6 7 8]
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function %uwidenlow_i16x8(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = uwiden_low v0
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return v1
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}
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; run: %uwidenlow_i16x8([1 2 3 4 5 6 7 8]) == [1 2 3 4]
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function %uwidenlow_i32x4(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = uwiden_low v0
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return v1
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}
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; run: %uwidenlow_i32x4([1 2 3 4]) == [1 2]
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@@ -824,8 +824,28 @@ where
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)?),
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Opcode::SwidenLow => unimplemented!("SwidenLow"),
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Opcode::SwidenHigh => unimplemented!("SwidenHigh"),
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Opcode::UwidenLow => unimplemented!("UwidenLow"),
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Opcode::UwidenHigh => unimplemented!("UwidenHigh"),
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Opcode::UwidenLow => {
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let new_type = ctrl_ty.merge_lanes().unwrap();
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let mut new_vec = SimdVec::new();
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let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?;
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arg0.truncate(new_type.lane_count() as usize);
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for lane in arg0 {
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let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?;
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new_vec.push(lane);
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}
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assign(vectorizelanes(&new_vec, new_type)?)
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}
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Opcode::UwidenHigh => {
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let new_type = ctrl_ty.merge_lanes().unwrap();
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let mut new_vec = SimdVec::new();
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let mut arg0 = extractlanes(&arg(0)?, ctrl_ty.lane_type())?;
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arg0.drain(0..new_type.lane_count() as usize);
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for lane in arg0 {
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let lane = lane.convert(ValueConversionKind::ZeroExtend(new_type.lane_type()))?;
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new_vec.push(lane);
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}
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assign(vectorizelanes(&new_vec, new_type)?)
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}
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Opcode::FcvtToUint => unimplemented!("FcvtToUint"),
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Opcode::FcvtToUintSat => unimplemented!("FcvtToUintSat"),
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Opcode::FcvtToSint => unimplemented!("FcvtToSint"),
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@@ -290,9 +290,14 @@ impl Value for DataValue {
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_ => unimplemented!("conversion: {} -> {:?}", self.ty(), kind),
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},
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ValueConversionKind::ZeroExtend(ty) => match (self, ty) {
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(DataValue::U8(n), types::I16) => DataValue::U16(n as u16),
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(DataValue::U8(n), types::I32) => DataValue::U32(n as u32),
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(DataValue::U8(n), types::I64) => DataValue::U64(n as u64),
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(DataValue::I8(n), types::I16) => DataValue::I16(n as u8 as i16),
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(DataValue::I8(n), types::I32) => DataValue::I32(n as u8 as i32),
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(DataValue::I8(n), types::I64) => DataValue::I64(n as u8 as i64),
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(DataValue::U16(n), types::I32) => DataValue::U32(n as u32),
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(DataValue::U16(n), types::I64) => DataValue::U64(n as u64),
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(DataValue::I16(n), types::I32) => DataValue::I32(n as u16 as i32),
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(DataValue::I16(n), types::I64) => DataValue::I64(n as u16 as i64),
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(DataValue::U32(n), types::I64) => DataValue::U64(n as u64),
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