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Add x86 SIMD sshr and ushr

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Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
This commit is contained in:
Andrew Brown
2019-10-07 10:38:35 -07:00
parent 808885ce56
commit f1904bffea
7 changed files with 197 additions and 2 deletions
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30
cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif
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@@ -19,3 +19,33 @@ ebb0(v0: i64x2 [%xmm6], v1: i64x2 [%xmm3]):
[-, %xmm6] v2 = x86_psll v0, v1 ; bin: 66 0f f3 f3
return v2
}
function %ushr_i16x8(i16x8, i64x2) -> i16x8 {
ebb0(v0: i16x8 [%xmm2], v1: i64x2 [%xmm1]):
[-, %xmm2] v2 = x86_psrl v0, v1 ; bin: 66 0f d1 d1
return v2
}
function %ushr_i32x4(i32x4, i64x2) -> i32x4 {
ebb0(v0: i32x4 [%xmm4], v1: i64x2 [%xmm0]):
[-, %xmm4] v2 = x86_psrl v0, v1 ; bin: 66 0f d2 e0
return v2
}
function %ushr_i64x2(i64x2, i64x2) -> i64x2 {
ebb0(v0: i64x2 [%xmm6], v1: i64x2 [%xmm3]):
[-, %xmm6] v2 = x86_psrl v0, v1 ; bin: 66 0f d3 f3
return v2
}
function %sshr_i16x8(i16x8, i64x2) -> i16x8 {
ebb0(v0: i16x8 [%xmm2], v1: i64x2 [%xmm1]):
[-, %xmm2] v2 = x86_psra v0, v1 ; bin: 66 0f e1 d1
return v2
}
function %sshr_i32x4(i32x4, i64x2) -> i32x4 {
ebb0(v0: i32x4 [%xmm4], v1: i64x2 [%xmm0]):
[-, %xmm4] v2 = x86_psra v0, v1 ; bin: 66 0f e2 e0
return v2
}