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Fix generated code for ISA predicates on encoding recipes.

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The generated code had syntax errors and inverted logic.

Add an SSE 4.1 requirement to the floating point rounding instructions.
This commit is contained in:
Jakob Stoklund Olesen
2017-12-08 10:22:01 -08:00
parent 362a4bdc4c
commit f03729d742
4 changed files with 14 additions and 8 deletions
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6
cranelift/filetests/isa/intel/binary32-float.cton
View File

@@ -1,6 +1,6 @@
; Binary emission of 32-bit floating point code.
test binemit
isa intel has_sse2
isa intel haswell
; The binary encodings can be verified with the command:
;
@@ -52,7 +52,7 @@ ebb0:
; asm: addss %xmm2, %xmm5
[-,%xmm5] v20 = fadd v10, v11 ; bin: f3 0f 58 ea
; asm: addss %xmm5, %xmm2
[-,%xmm2] v21 = fadd v11, v10 ; bin: f3 0f 58 d5
[-,%xmm2] v21 = fadd v11, v10 ; bin: f3 0f 58 d5
; asm: subss %xmm2, %xmm5
[-,%xmm5] v22 = fsub v10, v11 ; bin: f3 0f 5c ea
@@ -267,7 +267,7 @@ ebb0:
; asm: addsd %xmm2, %xmm5
[-,%xmm5] v20 = fadd v10, v11 ; bin: f2 0f 58 ea
; asm: addsd %xmm5, %xmm2
[-,%xmm2] v21 = fadd v11, v10 ; bin: f2 0f 58 d5
[-,%xmm2] v21 = fadd v11, v10 ; bin: f2 0f 58 d5
; asm: subsd %xmm2, %xmm5
[-,%xmm5] v22 = fsub v10, v11 ; bin: f2 0f 5c ea

2
cranelift/filetests/isa/intel/binary64-float.cton
View File

@@ -2,7 +2,7 @@
test binemit
set is_64bit
set is_compressed
isa intel has_sse2
isa intel haswell
; The binary encodings can be verified with the command:
;