Rename enc_flt() to enc_both().
This encoding method is not only used for floating point instructions.
This commit is contained in:
Jakob Stoklund Olesen
@@ -43,6 +43,24 @@ I64.legalize_type(
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# Helper functions for generating encodings.
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#
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def enc_i64(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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"""
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Add encodings for `inst` to I64 with and without a REX prefix.
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"""
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I64.enc(inst, *recipe.rex(*args, **kwargs))
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I64.enc(inst, *recipe(*args, **kwargs))
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def enc_both(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **Any) -> None
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"""
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Add encodings for `inst` to both I32 and I64.
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"""
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I32.enc(inst, *recipe(*args, **kwargs))
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enc_i64(inst, recipe, *args, **kwargs)
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def enc_i32_i64(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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"""
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@@ -82,22 +100,6 @@ def enc_i32_i64_ld_st(inst, w_bit, recipe, *args, **kwargs):
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I64.enc(inst.i64.any, *recipe(*args, **kwargs))
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def enc_flt(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **Any) -> None
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"""
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Add encodings for floating point instruction `inst` to both I32 and I64.
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"""
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I32.enc(inst, *recipe(*args, **kwargs))
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I64.enc(inst, *recipe.rex(*args, **kwargs))
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I64.enc(inst, *recipe(*args, **kwargs))
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def enc_i64(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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I64.enc(inst, *recipe.rex(*args, **kwargs))
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I64.enc(inst, *recipe(*args, **kwargs))
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for inst, opc in [
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(base.iadd, 0x01),
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(base.isub, 0x29),
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@@ -109,9 +111,9 @@ for inst, opc in [
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# Also add a `b1` encodings for the logic instructions.
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# TODO: Should this be done with 8-bit instructions? It would improve
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# partial register dependencies.
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enc_flt(base.band.b1, r.rr, 0x21)
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enc_flt(base.bor.b1, r.rr, 0x09)
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enc_flt(base.bxor.b1, r.rr, 0x31)
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enc_both(base.band.b1, r.rr, 0x21)
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enc_both(base.bor.b1, r.rr, 0x09)
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enc_both(base.bxor.b1, r.rr, 0x31)
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enc_i32_i64(base.imul, r.rrx, 0x0f, 0xaf)
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enc_i32_i64(x86.sdivmodx, r.div, 0xf7, rrr=7)
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@@ -119,7 +121,7 @@ enc_i32_i64(x86.udivmodx, r.div, 0xf7, rrr=6)
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enc_i32_i64(base.copy, r.umr, 0x89)
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enc_i32_i64(base.regmove, r.rmov, 0x89)
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enc_flt(base.regmove.b1, r.rmov, 0x89)
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enc_both(base.regmove.b1, r.rmov, 0x89)
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, rrr in [
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@@ -249,27 +251,27 @@ enc_i32_i64_ld_st(base.sload8, True, r.ldDisp32, 0x0f, 0xbe)
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# Float loads and stores.
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#
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enc_flt(base.load.f32.any, r.fld, 0x66, 0x0f, 0x6e)
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enc_flt(base.load.f32.any, r.fldDisp8, 0x66, 0x0f, 0x6e)
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enc_flt(base.load.f32.any, r.fldDisp32, 0x66, 0x0f, 0x6e)
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enc_both(base.load.f32.any, r.fld, 0x66, 0x0f, 0x6e)
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enc_both(base.load.f32.any, r.fldDisp8, 0x66, 0x0f, 0x6e)
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enc_both(base.load.f32.any, r.fldDisp32, 0x66, 0x0f, 0x6e)
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enc_flt(base.load.f64.any, r.fld, 0xf3, 0x0f, 0x7e)
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enc_flt(base.load.f64.any, r.fldDisp8, 0xf3, 0x0f, 0x7e)
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enc_flt(base.load.f64.any, r.fldDisp32, 0xf3, 0x0f, 0x7e)
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enc_both(base.load.f64.any, r.fld, 0xf3, 0x0f, 0x7e)
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enc_both(base.load.f64.any, r.fldDisp8, 0xf3, 0x0f, 0x7e)
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enc_both(base.load.f64.any, r.fldDisp32, 0xf3, 0x0f, 0x7e)
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enc_flt(base.store.f32.any, r.fst, 0x66, 0x0f, 0x7e)
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enc_flt(base.store.f32.any, r.fstDisp8, 0x66, 0x0f, 0x7e)
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enc_flt(base.store.f32.any, r.fstDisp32, 0x66, 0x0f, 0x7e)
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enc_both(base.store.f32.any, r.fst, 0x66, 0x0f, 0x7e)
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enc_both(base.store.f32.any, r.fstDisp8, 0x66, 0x0f, 0x7e)
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enc_both(base.store.f32.any, r.fstDisp32, 0x66, 0x0f, 0x7e)
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enc_flt(base.store.f64.any, r.fst, 0x66, 0x0f, 0xd6)
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enc_flt(base.store.f64.any, r.fstDisp8, 0x66, 0x0f, 0xd6)
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enc_flt(base.store.f64.any, r.fstDisp32, 0x66, 0x0f, 0xd6)
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enc_both(base.store.f64.any, r.fst, 0x66, 0x0f, 0xd6)
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enc_both(base.store.f64.any, r.fstDisp8, 0x66, 0x0f, 0xd6)
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enc_both(base.store.f64.any, r.fstDisp32, 0x66, 0x0f, 0xd6)
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enc_flt(base.fill.f32, r.ffiSib32, 0x66, 0x0f, 0x6e)
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enc_flt(base.fill.f64, r.ffiSib32, 0xf3, 0x0f, 0x7e)
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enc_both(base.fill.f32, r.ffiSib32, 0x66, 0x0f, 0x6e)
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enc_both(base.fill.f64, r.ffiSib32, 0xf3, 0x0f, 0x7e)
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enc_flt(base.spill.f32, r.fspSib32, 0x66, 0x0f, 0x7e)
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enc_flt(base.spill.f64, r.fspSib32, 0x66, 0x0f, 0xd6)
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enc_both(base.spill.f32, r.fspSib32, 0x66, 0x0f, 0x7e)
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enc_both(base.spill.f64, r.fspSib32, 0x66, 0x0f, 0xd6)
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#
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# Function addresses.
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@@ -307,10 +309,10 @@ enc_i32_i64(base.brnz, r.tjccd, 0x85)
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# Branch on a b1 value in a register only looks at the low 8 bits. See also
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# bint encodings below.
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enc_flt(base.brz.b1, r.t8jccb_abcd, 0x74)
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enc_flt(base.brz.b1, r.t8jccd_abcd, 0x84)
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enc_flt(base.brnz.b1, r.t8jccb_abcd, 0x75)
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enc_flt(base.brnz.b1, r.t8jccd_abcd, 0x85)
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enc_both(base.brz.b1, r.t8jccb_abcd, 0x74)
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enc_both(base.brz.b1, r.t8jccd_abcd, 0x84)
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enc_both(base.brnz.b1, r.t8jccb_abcd, 0x75)
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enc_both(base.brnz.b1, r.t8jccd_abcd, 0x85)
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#
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# Trap as ud2
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@@ -349,18 +351,18 @@ I64.enc(base.uextend.i64.i32, *r.umr(0x89))
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#
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# movd
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enc_flt(base.bitcast.f32.i32, r.frurm, 0x66, 0x0f, 0x6e)
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enc_flt(base.bitcast.i32.f32, r.rfumr, 0x66, 0x0f, 0x7e)
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enc_both(base.bitcast.f32.i32, r.frurm, 0x66, 0x0f, 0x6e)
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enc_both(base.bitcast.i32.f32, r.rfumr, 0x66, 0x0f, 0x7e)
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# movq
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I64.enc(base.bitcast.f64.i64, *r.frurm.rex(0x66, 0x0f, 0x6e, w=1))
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I64.enc(base.bitcast.i64.f64, *r.rfumr.rex(0x66, 0x0f, 0x7e, w=1))
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# movaps
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enc_flt(base.copy.f32, r.furm, 0x0f, 0x28)
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enc_flt(base.copy.f64, r.furm, 0x0f, 0x28)
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enc_flt(base.regmove.f32, r.frmov, 0x0f, 0x28)
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enc_flt(base.regmove.f64, r.frmov, 0x0f, 0x28)
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enc_both(base.copy.f32, r.furm, 0x0f, 0x28)
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enc_both(base.copy.f64, r.furm, 0x0f, 0x28)
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enc_both(base.regmove.f32, r.frmov, 0x0f, 0x28)
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enc_both(base.regmove.f64, r.frmov, 0x0f, 0x28)
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# cvtsi2ss
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enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)
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@@ -369,22 +371,22 @@ enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)
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enc_i32_i64(base.fcvt_from_sint.f64, r.frurm, 0xf2, 0x0f, 0x2a)
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# cvtss2sd
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enc_flt(base.fpromote.f64.f32, r.furm, 0xf3, 0x0f, 0x5a)
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enc_both(base.fpromote.f64.f32, r.furm, 0xf3, 0x0f, 0x5a)
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# cvtsd2ss
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enc_flt(base.fdemote.f32.f64, r.furm, 0xf2, 0x0f, 0x5a)
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enc_both(base.fdemote.f32.f64, r.furm, 0xf2, 0x0f, 0x5a)
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# cvttss2si
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enc_flt(x86.cvtt2si.i32.f32, r.rfurm, 0xf3, 0x0f, 0x2c)
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enc_both(x86.cvtt2si.i32.f32, r.rfurm, 0xf3, 0x0f, 0x2c)
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I64.enc(x86.cvtt2si.i64.f32, *r.rfurm.rex(0xf3, 0x0f, 0x2c, w=1))
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# cvttsd2si
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enc_flt(x86.cvtt2si.i32.f64, r.rfurm, 0xf2, 0x0f, 0x2c)
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enc_both(x86.cvtt2si.i32.f64, r.rfurm, 0xf2, 0x0f, 0x2c)
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I64.enc(x86.cvtt2si.i64.f64, *r.rfurm.rex(0xf2, 0x0f, 0x2c, w=1))
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# Exact square roots.
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enc_flt(base.sqrt.f32, r.furm, 0xf3, 0x0f, 0x51)
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enc_flt(base.sqrt.f64, r.furm, 0xf2, 0x0f, 0x51)
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enc_both(base.sqrt.f32, r.furm, 0xf3, 0x0f, 0x51)
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enc_both(base.sqrt.f64, r.furm, 0xf2, 0x0f, 0x51)
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# Rounding. The recipe looks at the opcode to pick an immediate.
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for inst in [
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@@ -392,8 +394,8 @@ for inst in [
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base.floor,
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base.ceil,
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base.trunc]:
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enc_flt(inst.f32, r.furmi_rnd, 0x66, 0x0f, 0x3a, 0x0a, isap=use_sse41)
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enc_flt(inst.f64, r.furmi_rnd, 0x66, 0x0f, 0x3a, 0x0b, isap=use_sse41)
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enc_both(inst.f32, r.furmi_rnd, 0x66, 0x0f, 0x3a, 0x0a, isap=use_sse41)
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enc_both(inst.f64, r.furmi_rnd, 0x66, 0x0f, 0x3a, 0x0b, isap=use_sse41)
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# Binary arithmetic ops.
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@@ -404,24 +406,24 @@ for inst, opc in [
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(base.fdiv, 0x5e),
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(x86.fmin, 0x5d),
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(x86.fmax, 0x5f)]:
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enc_flt(inst.f32, r.fa, 0xf3, 0x0f, opc)
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enc_flt(inst.f64, r.fa, 0xf2, 0x0f, opc)
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enc_both(inst.f32, r.fa, 0xf3, 0x0f, opc)
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enc_both(inst.f64, r.fa, 0xf2, 0x0f, opc)
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# Binary bitwise ops.
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for inst, opc in [
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(base.band, 0x54),
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(base.bor, 0x56),
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(base.bxor, 0x57)]:
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enc_flt(inst.f32, r.fa, 0x0f, opc)
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enc_flt(inst.f64, r.fa, 0x0f, opc)
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enc_both(inst.f32, r.fa, 0x0f, opc)
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enc_both(inst.f64, r.fa, 0x0f, opc)
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# The `andnps(x,y)` instruction computes `~x&y`, while band_not(x,y)` is `x&~y.
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enc_flt(base.band_not.f32, r.fax, 0x0f, 0x55)
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enc_flt(base.band_not.f64, r.fax, 0x0f, 0x55)
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enc_both(base.band_not.f32, r.fax, 0x0f, 0x55)
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enc_both(base.band_not.f64, r.fax, 0x0f, 0x55)
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# Comparisons.
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#
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# This only covers the condition codes in `supported_floatccs`, the rest are
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# handled by legalization patterns.
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enc_flt(base.fcmp.f32, r.fcscc, 0x0f, 0x2e)
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enc_flt(base.fcmp.f64, r.fcscc, 0x66, 0x0f, 0x2e)
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enc_both(base.fcmp.f32, r.fcscc, 0x0f, 0x2e)
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enc_both(base.fcmp.f64, r.fcscc, 0x66, 0x0f, 0x2e)
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