[meta] Introduce the InstructionGroupBuilder;

This follows the rest of the code base data structures, where we have a
mutable data structure builder; once the data structure is constructed,
it's immutable.

This also makes the definition of instructions easier, and it paves the
way for defining immediate variants.
This commit is contained in:
Benjamin Bouvier
2019-04-30 18:33:01 +02:00
parent feb90e376a
commit d9277f249b
7 changed files with 251 additions and 382 deletions

View File

@@ -1,5 +1,5 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::instructions::InstructionGroup;
use crate::cdsl::instructions::InstructionGroupBuilder;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
@@ -52,7 +52,12 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let settings = define_settings(&shared_defs.settings);
let regs = define_regs();
let inst_group = InstructionGroup::new("arm32", "arm32 specific instruction set");
let inst_group = InstructionGroupBuilder::new(
"arm32",
"arm32 specific instruction set",
&shared_defs.format_registry,
)
.finish();
// CPU modes for 32-bit ARM and Thumb2.
let mut a32 = CpuMode::new("A32");

View File

@@ -1,5 +1,5 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::instructions::InstructionGroup;
use crate::cdsl::instructions::InstructionGroupBuilder;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
@@ -48,7 +48,12 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let settings = define_settings(&shared_defs.settings);
let regs = define_registers();
let inst_group = InstructionGroup::new("arm64", "arm64 specific instruction set");
let inst_group = InstructionGroupBuilder::new(
"arm64",
"arm64 specific instruction set",
&shared_defs.format_registry,
)
.finish();
let mut a64 = CpuMode::new("A64");

View File

@@ -1,5 +1,5 @@
use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::instructions::InstructionGroup;
use crate::cdsl::instructions::InstructionGroupBuilder;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
@@ -86,7 +86,12 @@ pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
let settings = define_settings(&shared_defs.settings);
let regs = define_registers();
let inst_group = InstructionGroup::new("riscv", "riscv specific instruction set");
let inst_group = InstructionGroupBuilder::new(
"riscv",
"riscv specific instruction set",
&shared_defs.format_registry,
)
.finish();
// CPU modes for 32-bit and 64-bit operation.
let mut rv_32 = CpuMode::new("RV32");

View File

@@ -1,14 +1,17 @@
#![allow(non_snake_case)]
use crate::cdsl::formats::FormatRegistry;
use crate::cdsl::instructions::{InstructionBuilder as Inst, InstructionGroup};
use crate::cdsl::instructions::{
InstructionBuilder as Inst, InstructionGroup, InstructionGroupBuilder,
};
use crate::cdsl::operands::{create_operand as operand, create_operand_doc as operand_doc};
use crate::cdsl::types::ValueType;
use crate::cdsl::typevar::{Interval, TypeSetBuilder, TypeVar};
use crate::shared::types;
pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
let mut ig = InstructionGroup::new("x86", "x86 specific instruction set");
let mut ig =
InstructionGroupBuilder::new("x86", "x86 specific instruction set", format_registry);
let iflags: &TypeVar = &ValueType::Special(types::Flag::IFlags.into()).into();
@@ -39,8 +42,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
)
.operands_in(vec![nlo, nhi, d])
.operands_out(vec![q, r])
.can_trap(true)
.finish(format_registry),
.can_trap(true),
);
ig.push(
@@ -59,8 +61,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
)
.operands_in(vec![nlo, nhi, d])
.operands_out(vec![q, r])
.can_trap(true)
.finish(format_registry),
.can_trap(true),
);
let argL = &operand("argL", iWord);
@@ -79,8 +80,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![argL, argR])
.operands_out(vec![resLo, resHi])
.finish(format_registry),
.operands_out(vec![resLo, resHi]),
);
ig.push(
@@ -94,8 +94,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![argL, argR])
.operands_out(vec![resLo, resHi])
.finish(format_registry),
.operands_out(vec![resLo, resHi]),
);
let Float = &TypeVar::new(
@@ -131,8 +130,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![x])
.operands_out(vec![a])
.finish(format_registry),
.operands_out(vec![a]),
);
let x = &operand("x", Float);
@@ -154,8 +152,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![x, y])
.operands_out(vec![a])
.finish(format_registry),
.operands_out(vec![a]),
);
ig.push(
@@ -173,8 +170,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![x, y])
.operands_out(vec![a])
.finish(format_registry),
.operands_out(vec![a]),
);
let x = &operand("x", iWord);
@@ -193,8 +189,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
)
.operands_in(vec![x])
.other_side_effects(true)
.can_store(true)
.finish(format_registry),
.can_store(true),
);
ig.push(
@@ -212,8 +207,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
)
.operands_out(vec![x])
.other_side_effects(true)
.can_load(true)
.finish(format_registry),
.can_load(true),
);
let y = &operand("y", iWord);
@@ -233,8 +227,7 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![x])
.operands_out(vec![y, rflags])
.finish(format_registry),
.operands_out(vec![y, rflags]),
);
ig.push(
@@ -246,9 +239,8 @@ pub fn define(format_registry: &FormatRegistry) -> InstructionGroup {
"#,
)
.operands_in(vec![x])
.operands_out(vec![y, rflags])
.finish(format_registry),
.operands_out(vec![y, rflags]),
);
ig
ig.finish()
}